A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1711-1718

  Kirihata, Toshiaki ^a,c,d,e,f,g   Gall, Martin ^a,h,i   Hosokawa, Kohji ^a,f,j   Dortu, Jean Marc ^a,h,i,k,l   Wong, Hing ^a,b,m   Pfefferl, Peter ^a,h,n,o   Ji, Brian L ^a,p,q,r,s   Weinfurtner, Oliver ^a,h,t   DeBrosse, John K ^a,u   Terletzki, Hartmud ^a   Selz, Manfred ^a   Ellis, Wayne ^a   Wordeman, Matthew R ^a,b   Kiehl, Oliver ^a  

^a IBM   (United States)

^b IEEE

^c SHINSHU UNIVERSITY   (Japan)

^d IBM RESEARCH   (United States)

^e IBM T J WATSON RESEARCH CENTER   (United States)

^f IBM JAPAN LTD   (Japan)

^g Institute of Electronics   (Japan)

^h SIEMENS AG   (Germany)

ⁱ TOSHIBA CORPORATION   (Japan)

^j HIROSHIMA UNIVERSITY   (Japan)

^k ECOLE CENTRALE PARIS   (France)

^l UNIV LILLE   (France)

^m UNIVERSITY OF CALIFORNIA   (United States)

ⁿ UNIVERSITY OF KASSEL   (Germany)

^o IBM Japan Ltd ^*

^p UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^q HARVARD UNIVERSITY   (United States)

^r STONY BROOK UNIVERSITY   (United States)

^s IBM MICROELECTRONICS   (United States)

^t UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^u PURDUE UNIVERSITY   (United States)

more..

Author keywords

256 Mb DRAM; 256 Mb SDRAM; Asymmetric block activation; Divided column redundancy; DRAM; Flexible test mode; Frequency doubling test mode; Intraunit address increment; Memory; SDRAM; Selectable redundancy; Single ended RWD; Stitched WL architecture; Trench cell

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

SINGLE-SIDED STITCHED WORD LINE ARCHITECTURES; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032205692     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726565     Document Type: Article

References (31)

1. N. C. C. Lu, G. B. Bronner, K. Kitamura, R. E. Scheuerlein, W. H. Henkels, S. H. Dhong, Y. Katayama, T. Kirihata, N. Niijima, R. L. French, W. Hwang, M. Nishiwaki, F. L. Pesavento, T. V. Rajeevakumar, Y. Sakaue, Y. Suzuki, Y. Iguchi, and E. Yano, "A 22 ns 1 Mb CMOS high-speed DRAM with address multiplexing," IEEE J. Solid-State Circuits, vol. 24, pp. 1198-1205, Sept. 1992.
2. T. Kirihata, S. H. Dhong, K. Kitamura, T. Sunaga, Y. Katayama, R. R. Scheuerlein, K. Hosokawa, T. Saitoh, T. Yoshikawa, H. Hashimoto, and M. Kazusawa, "A 14 ns 4 Mb DRAM with 300 mW active power." IEEE J. Solid-State Circuits, vol. 27, pp. 1222-1228, Sept. 1992.
3. S. Fujii, M. Ogihara, M. Shimizu, M. Yoshida, K. Numata, T. Hara, S. Watanabe, S. Sawada, T. Mizuno, J. Kumagai, S. Yoshikawa, S. Kaki, Y. Saito, H. Aochi, T. Hamamoto, and K. Toita, "A 45-ns 16-Mbit DRAM with triple-well structure," IEEE J. Solid-State Circuits, vol. 24, pp. 1170-1175, Oct. 1989.
4. T. Saeki, N. Yuji, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itami, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, K. Koyama, Y. Fukuzo, and T. Okuda, "A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay," in 1996 IEEE ISSCC Dig. Tech. Papers, pp. 374-375.
5. J.-H. Yoo, C.-H. Kirn, K.-C. Lee, K.-H. Kyung, S.-M. Yoo, J.-H. Lee, M.-H. Son, J.-M. Han, B.-M. Kang, E. Haq, S.-B. Lee, J.-G. Park, K.-P. Lee, K.-Y. Lee, K.-N. Kim, S.-I. Cho, J.-W. Park, and H.-K. Lim, "A 32-bank 1 Gb DRAM with 1 GB/s bandwidth," in 1996 IEEE ISSCC Dig. Tech. Papers, pp. 378-379.
6. S. Eto, M. Matsuyima, M. Takita, Y. Ishii, T. Nakamura, K. Kawabata, H. Kano, A. Kitamoto, T. Ikeda, T. Koga, M. Higashino, Y. Serizawa, K. Itabashi, O. Tsuboi, Y. Yokoyama, and M. Taguchi, "A 1 Gb SDRAM with ground level precharged bitline and nonboosted 2.1 V word line," in 1998 IEEE ISSCC Dig. Tech. Papers, pp. 82-83.
7. T. Murotani, I. Naritake, T. Matano, T. Ohtsuki, N. Kasai, H. Koga, K. Koyama, K. Nakajima, H. Yamaguchi, H. Watanabe, and T. Okuda, "A 4-level storage 4 Gb DRAM," in 1997 IEEE ISSCC Dig. Tech. Papers, pp. 74-75.
8. 2 MIM_CROWN cell and process technologies for 1-Gb DRAM's," in IEDM Tech. Dig., Dec. 1994, pp. 927-932.
9. T. Murotani, T. Takahashi, T. Akiba, G. Kitsukawa, M. Morino, T. Sekiguchi, I. Asano, K. Komatsuzaki, Y. Tadaki, S. Cho, K. Kajigaya, T. Tachibana, and K. Sato. "A 29-ns 64-Mb DRAM with hierarchical array architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 1302-1307, Sept. 1996.
10. 2 256 Mb trench DRAM cell with self-aligned BuriEd STrap," in IEDM Tech. Dig., Dec. 1993, pp. 627-630.
11. G. Bronner, H. Aochi, M. Gall, J. Gambino, S. Gerhardt, E. Hammer, H. Ho, J. Iba, H. Ishiuchi, M. Jaso, R. Kleinhenz, T. Mii, M. Narita, L. Nesbit, W. Neumuller, A. Nitayama, T. Ohiwa, S. Parke, J. Ryan, T. Sato, H. Takato, and S. Yoshikawa, "A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond," in Symp. 1995 VLSI Technologies Dig. Tech. Papers, pp. 15-16.
12. 2 256 Mb DRAM with ×32 both ends DQ," IEEE J. Solid-State Circuits, vol. 31, pp. 567-574, Apr. 1996.
13. T. Kirihata, Y. Watanabe, H. Wong, J. K. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. R. Wordeman, P. Poechmuller, S. A. Parke, and Y. Asao, "A fault-tolerant designs for 256 Mb DRAM," IEEE J. Solid-State Circuits, vol. 31, pp. 558-566, Apr. 1996.
14. 2 256 Mb SDRAM with single-sided stitched WL architecture," in 1998 IEEE ISSCC Dig Tech. Papers, pp. 78-79.
15. M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma, Y. Kawase, H. Endoh, S. Miyatake, T. Akiba, K. Kawakita, M. Yoshida, S. Yamada, T. Sekiguchi, I. Asano, Y. Tadki, R. Nagai, S. Miyaoka, K. Kajigaym, M. Horiguchi, and Y. Nakagome, "A 256 Mb SDRAM with subthreshold leakage current suppression," in 1998 IEEE ISSCC Dig. Tech. Papers, pp. 80-81.
16. J.-M. Han, J.-B. Lee, S.-S. Yoon, S.-J. Jeong, C. Park, I.-J. Cho, S.-H. Lee, and D.-I. Seo. "Skew minimization techniques for 256 M-bit synchronous DRAM and beyond," in Symp. 1996 on VLSI Circuits, Dig. Tech. Papers, pp. 192-193.
17. S.-J. Lee, K.-W. Park, C.-H. Chung, J.-S. Son, K.-H. Park, S.-H. Shin, S.-T. Kim, J.-D. Han, H.-J. Yoo, W.-S. Min, and K.-H. Oh, "A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O Line," in Symp. 1995 VLSI Circuits Dig Tech. Papers, pp 113-114.
18. T. Sakata, M. Horiguchi, T. Sekiguchi, S. Ueda, H. Tanaka, E. Yamasaki, Y. Nakagome, M. Aoki, T. Kaga, M. Ohkura, R. Nagai, F. Murai, T. Tanaka, S. Iijima, N. Yokoyama, Y. Gotoh, K. Shoji, T. Kisu, H. Yamashita, T. Nishida, and E. Takeda, "An experimental 220 MHz 1 Gb DRAM with a distributed-column-control architecture," IEEE J. Solid-State Circuits, vol. 30, pp. 1165-1173, Nov. 1995.
19. C. Kim, J. Lee, B. Kim, C. Park, S. Lee, C. Park, J. Roh, H. Nam, D. Kim, T. Jung, and S. Cho, "A 640 MB/s bi-directional data strobed, double-data-rate SFRAM with a 40 mW DLL circuit for a 256 MB memory system," in 1998 IEEE ISSCC Dig. Tech. Papers, pp. 158-159.
20. T. Sunaga, K. Hosokawa, Y. Nakamura, M. Ichinose, A. Moriwaki, S. Kakimi, and N. Kato, "A full bit prefetch architecture for synchronous DRAM'S," IEEE J. Solid-State Circuits, vol. 30, pp. 998-1005, Sept. 1995.
21. N. Kushiyama, S. Ohshima, D. Stark, H. Niji, K. Sakurai, S. Takase, T. Furuyama, R. M. Barth, A. Chan, J. Dillon, J. A. Gasbarro, M. M. Griffin, M. Horowitz, T. H. Lee, and V. Lee, "500 Mbyte/sec data-rate 512 Kbits ×9 DRAM," IEEE J. Solid-State Circuits, vol. 28, pp. 490-498, Apr. 1993.
22. M. Griffin, J. Zerbe, A. Chan, Y.-H. Jun, Y. Tanaka, W. Richardson, G. Tsang, M. Ching, C. Portmann, Y. Li, B. Stonecypher, L. Lai, K.-H. Lee, V. Lee, D. Stark, H. Modarres, P. Barta, J. L. Chanfran, J. Privitera, T. Thrush, B. Nickel, J. Yang, V. Hennon, and R. Sauv, "A process independent 800 MB/s DRAM byte-wide interface featuring command interleaving and concurrent memory operation," in 1998 IEEE ISSCC Dig. Tech. Papers, pp. 156-157.
23. Y. Takai, M. Nagase, M. Kitamura, Y. Koshikawa, N. Yoshida, Y. Kobayashi, T. Obara, Y. Fukuzo, and H. Watanabe, "250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture," in Symp. 1993 VLSI Circuits Dig. Tech. Papers, pp. 59-60.
24. A. Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, and T. Ema, "A 150-MHz 4-bank 64 Mb SDRAM with address incrementing pipeline scheme," in Symp. 1994 VLSI Circuits Dig. Tech. Papers, pp. 81-82.
25. M. Taguchi, H. Tomita, T. Uchida, Y. Ohnishi, K. Sato, T. Ema, M. Higashitani, and T. Yabe, "A 40 ns 64 Mb DRAM with 64 b parallel data bus architecture," IEEE J. Solid-State Circuits, vol. 26, pp. 1493-1497, Nov. 1991.
26. T. Kirihata, H. Wong, J. K. DeBrosse, Y. Watanabe, T. Hara, M. Yoshida, M. R. Wordeman, S. Fujii, Y. Asao, and B. Krsnik, "A flexible test mode approach for 256-Mb DRAM," IEEE J. Solid-State Circuits, vol. 32, pp. 1525-1534, Oct. 1997.
27. H.-J. Song, J.-P. Kim, J.-J. Lee, J.-H. Oh, S.-H. Ahn, and I. Hwang, "A 200-MHz register-based wave-pipelined 64 Mb synchronous DRAM," IEEE J. Solid-State Circuits, vol. 32, pp. 92-99, Jan. 1997.
28. S.-M. Yoo, J. M. Han, E. Haq, S. S. Yoon, S.-J. Jeong, B. C. Kim, J.-H. Lee, T.-S. Jang, H.-D. Kim, C. J. Park, D. I. Seo, C. S. Choi, S.-I. Cho, and C. G. Hwang, "A 256 M DRAM with simplified register control for low power self refresh and rapid burn-in," in Symp. 1994 VLSI Circuits, Dig. Tech. Papers, pp. 85-86.
29. H. L. Kalter, C. H. Stapper, J. E. Barth, Jr., J. Dilorenzo, C. Drake, J. A. Fitfield, G. A. Kelley, Jr., S. C. Lewis, W. B. Van Der Hoeven, and J. A. Yankosky, "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC," IEEE J. Solid-State Circuits, vol. 25, pp. 1118-1128, Oct. 1990.
30. T. Sugibayashi, T. Takeshima, I. Naritake, T. Matano, H. Takada, Y. Aimoto, K. Furuta, M. Fujita, T. Saeki, H. Sugawara, T. Murouni, N. Kasai, K. Shibahara, K. Nakajima, H. Hada, T. Hamda, N. Aizaki, T. Kunio, E. Kakehashi, K. Masumori, and T. Tanigawa, "A 30 ns 256 Mb DRAM with multi-divided array structure," IEEE J. Solid-State Circuits. vol. 28, pp. 1092-1098, Nov. 1993.
31. D. Galbi et al., "A 33-ns 64 Mb DRAM with master word line architecture," in ESSCIRC Dig. Tech. Papers. 1992, pp. 131-344.