32-bank 1Gb DRAM with 1GB/s bandwidth

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 378-379

  Yoo, Jei Hwan ^a   Kim, Chang Hyun ^a   Lee, Kyu Chan ^a   Kyung, Kye Hyun ^a   Yoo, Seung Moon ^a   Lee, Jung Hwa ^a   Son, Moon Hae ^a   Han, Jin Man ^a   Kang, Bok Moon ^a   Haq, Ejaz ^a   Lee, Sang Bo ^a   Sim, Jai Hoon ^a   Kim, Joung Ho ^a   Moon, Byung Sik ^a   Kim, Keum Yong ^a   et al , ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ARRAYS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DECODING; FREQUENCY MULTIPLYING CIRCUITS; INPUT OUTPUT PROGRAMS; PHASE LOCKED LOOPS;

GLOBAL COLUMN SELECTION LINES; LOCAL COLUMN SELECTION LINES; OPTICAL LITHOGRAPHY; PARALLEL IN SERIAL OUT REGISTER; PEAK DATA BANDWIDTH; PERIPHERAL CIRCUIT; READ WRITE INFORMATION; SENSE AMPLIFIERS; SERIAL IN PARALLEL OUT REGISTER;

RANDOM ACCESS STORAGE;

EID: 0030081189     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)