1 Gb SDRAM with ground level precharged bitline and non-boosted 2.1 V word line

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 82-83,-419

  Eto, Satoshi ^a   Matsumiya, Masato ^a   Takita, Masato ^a   Ishii, Yuki ^a   Nakamura, Toshikazu ^a   Kawabata, Kuninori ^a   Kano, Hideki ^a   Kitamoto, Ayako ^a   Ikeda, Toshimi ^a   Higashiho, Mitsuhiro ^a   Serizawa, Yuji ^a   Itabashi, Kazuo ^a   Tsuboi, Osamu ^a   Yokoyama, Yuji ^a   Taguchi, Masao ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS;

DELAY LOCKED LOOP (DLL); DYNAMIC RANDOM ACCESS MEMORY (DRAM); SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

RANDOM ACCESS STORAGE;

EID: 0031704596     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)