150-MHz 4-bank 64 M-bit SDRAM with address incrementing pipeline scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1994, Pages 81-82

  Kodama, Yukinori ^a   Yanagisawa, Makoto ^a   Shigenobu, Katsumi ^a   Suzuki, Takaaki ^a   Mochizuki, Hirohiko ^a   Ema, Taiji ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CRITICAL PATH ANALYSIS; DATA TRANSFER; ELECTRIC WAVEFORMS; ELECTRONICS PACKAGING; INTERFACES (COMPUTER); LOGIC DESIGN; MICROPROGRAMMING; PIPELINE PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER); TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

ADDRESS INCREMENTING PIPELINE SCHEME; COLUMN ACCESS PATH; READ AND WRITE OPERATIONS; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES;

RANDOM ACCESS STORAGE;

EID: 0028555449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)