250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture

1993 Symposium on VLSI Circuits Digest of Technical Papers

Volumn , Issue , 1993, Pages 59-60

  Takai, Y ^a   Nagase, M ^a   Kitamura, M ^a   Koshikawa, Y ^a   Yoshida, N ^a   Kobayashi, Y ^a   Obara, T ^a   Fukuzo, Y ^a   Watanabe, H ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

ADDRESS-ACCESS PATH; DYNAMIC RANDOM ACCESS MEMORY (DRAM); SYNCHRONOUS DRAM; THREE-STAGE PIPELINED ARCHITECTURE;

RANDOM ACCESS STORAGE;

EID: 0027812844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsic.1993.920536     Document Type: Conference Paper

References (2)