2.5ns clock access 250MHz 256Mb SDRAM with a synchronous mirror delay

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 374-375

  Saeki, Takanori ^a   Nakaoka, Yuji ^a   Fujita, Mamoru ^a   Tanaka, Akihito ^a   Nagata, Kyoichi ^a   Sakakibara, Kenichi ^a   Matano, Tatsuya ^a   Hoshino, Yukio ^a   Miyano, Kazutaka ^a   Isa, Satoshi ^a   Kakehashi, Eiichiro ^a   Drynan, John Mark ^a   Komuro, Masahiro ^a   Fukase, Tadashi ^a   Iwasaki, Haruo ^a   et al , ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ARRAYS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; MOS DEVICES; PHASE LOCKED LOOPS; READOUT SYSTEMS; SWITCHES;

DUAL WORLD LINE; MAXIMUM CLOCK FREQUENCY; PARALLEL SERIAL CONVERTER; PREFETCHED PIPELINE SCHEME; READ WRITE DATA BUS; SYNCHRONOUS MIRROR DELAY CIRCUIT;

RANDOM ACCESS STORAGE;

EID: 0030083363     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)