Flexible test mode approach for 256-Mb DRAM

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 10, 1997, Pages 1525-1532

  Kirihata, Toshiaki ^a,b,c   Wong, Hing ^a,b   DeBrosse, John K ^b   Watanabe, Yohji ^a,b,d   Hara, Takahiko ^b   Yoshida, Munehiro ^a,b   Wordeman, Matthew R ^a,b   Fujii, Shuso ^b,d   Asao, Yoshiaki ^b,d   Krsnik, Bo ^b  

^a IEEE   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d TOSHIBA CORPORATION   (Japan)

Author keywords

256 Mb DRAM; Disturb test; DRAM; External control; Flexible test mode; Multiwordline select; Retention test; Signal margin; Stress test; Test mode; VLSI

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; RANDOM ACCESS STORAGE; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

DYNAMIC RANDOM ACCESS MEMORY; FLEXIBLE TEST MODE; SIGNAL MARGIN; TRANSFER GATE STRESS VOLTAGE TEST; WORDLINE DISTURB TEST;

INTEGRATED CIRCUIT TESTING;

EID: 0031258266     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634660     Document Type: Article

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