Fault-tolerant designs for 256 Mb DRAM

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 558-565

  Kirihata, Toshiaki ^a,b,c,d,e,f   Watanabe, Yohji ^a,b,g,h   Wong, Hing ^a,b,i   DeBrosse, John K ^b,j   Yoshida, Munehiro ^a,b,g,h   Kato, Daisuke ^b,h,k   Fujii, Shuso ^b,h,l,m,n   Wordeman, Matthew R ^b   Poechmueller, Peter ^b   Parke, Stephen A ^b   Asao, Yoshiaki ^b  

^a IEEE

^b IBM   (United States)

^c SHINSHU UNIVERSITY   (Japan)

^d IBM RESEARCH   (United States)

^e IBM T J WATSON RESEARCH CENTER   (United States)

^f Info Commun E

^g TOHOKU UNIVERSITY   (Japan)

^h TOSHIBA CORPORATION   (Japan)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j PURDUE UNIVERSITY   (United States)

^k KEIO UNIVERSITY   (Japan)

^l SHIZUOKA UNIVERSITY   (Japan)

^m UNIVERSITY OF TOKYO   (Japan)

ⁿ SIEMENS AG   (Germany)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA COMPRESSION; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; LIMITERS; LITHOGRAPHY; MOS DEVICES; PERSONAL COMPUTERS; REDUNDANCY; SHORT CIRCUIT CURRENTS;

ERROR CORRECTION CODE; INTERCHANGEABLE MASTER; REDUNDANT BITLINES; REDUNDANT WORDLINES;

RANDOM ACCESS STORAGE;

EID: 0030123706     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499733     Document Type: Article

References (27)

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