220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 78-79,-417

  Kirihata, T ^a   Gall, M ^a   Hosokawa, K ^a   Dortu, J M ^a   Wong, H ^a   Pfefferl, K P ^a   Ji, B ^a   Weinfurtner, O ^a   DeBrosse, J ^a   Terletzki, H ^a   Selz, M ^a   Ellis, W ^a   Wordeman, M ^a   Kiehl, O ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

READ WRITE DRIVES (RWD); SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM); WORDLINE (WL) ARCHITECTURE;

RANDOM ACCESS STORAGE;

EID: 0031655618     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)