A 286 mm2 256 Mb DRAM with × 32 both-ends DQ

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 567-573

  Watanabe, Yohji ^a,b   Wong, Hing ^a,b   Kirihata, Toshiaki ^a,b   Kato, Daisuke ^b   DeBrosse, John K ^b   Hara, Takahiko ^b,d,e   Yoshida, Munehiro ^a,b   Mukai, Hideo ^b,e,f   Quader, Khandker N ^{a,b,c,g,h,i,j,k}   Nagai, Takeshi ^b   Poechmueller, Peter ^b   Pfefferl, Peter ^b   Wordeman, Matthew R ^b   Fujii, Shuso ^b  

^a IEEE

^b IBM   (United States)

^c SanDisk Corporation   (United States)

^d HOKKAIDO UNIVERSITY   (Japan)

^e TOSHIBA CORPORATION   (Japan)

^f UNIVERSITY OF TOKYO   (Japan)

^g MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^h GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j INTEL CORPORATION   (United States)

^k IBM MICROELECTRONICS   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STRUCTURES; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PERSONAL COMPUTERS;

ACCESS; ADDRESS BUS; EXCHANGEABLE HIERARCHICAL DATA LINE STRUCTURE; ROW ADDRESS STROBE;

RANDOM ACCESS STORAGE;

EID: 5844391766     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499734     Document Type: Article

References (8)

1. M. Taguchi et al., "A 40 Ms 64 Mb DRAM with 64b parallel data bus architecture," IEEE J. Solid-State Circuits, vol. 26, pp. 1493-1497, Nov. 1991.
2. K. Komatsuzaki et al., "Circuit techniques for a wide I/O path 64 Meg DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 1991, pp. 133-134.
3. T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with multi-divided array structure," IEEE J. Solid-State Circuits, vol. 28, pp. 1092-1098, 1993.
4. S. Yoo et al., "A 256 M DRAM with simplified register control for low power self refresh and rapid burn-in," in Symp. VLSI Circuits Dig. Tech. Papers, June 1994, pp. 85-86.
5. 2 256 M DRAM with ×32 both-ends DQ," in Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 105-106.
6. T. Kirihata et al., "Fault-tolerant designs for 256 Mb DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 107-108.
7. 2 256 Mb trench DRAM cell with self-aligned BuriEd STrap," in IEDM Dig. Tech. Papers, pp. 627-630, Dec. 1993.
8. G. Bronner et al., "A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond," in Symp. VLSI Technologies Dig. Tech. Papers, June 1995, pp. 15-16.