A 200 MHz register-based wave-pipelined 64M synchronous DRAM

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 1, 1997, Pages 92-99

  Song, Ho Jun ^a   Kim, Jung Pill ^b   Lee, Jae Jin ^b   Oh, Jong Hoon ^b   Ahn, Seung Han ^b   Hwang, Inseok ^b  

^a Chungnam National University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CRITICAL PATH ANALYSIS; SHIFT REGISTERS; TIMING CIRCUITS;

BURST READ OPERATION; COLUMN ADDRESS STROBE (CAS) LATENCY; DATA BUS LINE PAIR; INTERNAL TIMING MARGIN; REGISTER BASED WAVE PIPELINE SCHEME; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

RANDOM ACCESS STORAGE;

EID: 0030837293     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.553186     Document Type: Article

References (11)

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