640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 158-159

  Kim, C ^a   Lee, J ^a,a   Kim, B ^a   Park, C ^a,a   Lee, S ^a,a   Roh, J ^a   Nam, H ^a   Kim, D ^a   Jung, T ^a   Cho, S ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; TIMING CIRCUITS;

BIDIRECTIONAL DATA STROBED DOUBLE DATA RATE (BDDR); DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0031655480     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)