Partial-scan delay fault testing of asynchronous circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 11, 1998, Pages 1184-1199

  Kishinevsky, Michael ^a,b,c,d   Kondratyev, Alex ^a,b,c,d   Lavagno, Luciano ^a,b,c,d   Saldanha, Alex ^a,b,c,d   Taubin, Alexander ^a,b,c,d  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF AIZU   (Japan)

^c POLITECNICO DI TORINO   (Italy)

^d CADENCE DESIGN SYSTEMS   (United States)

Author keywords

asynchronous circuits; Delay fault testing; Partial scan

Indexed keywords

COMBINATORIAL CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING;

ASYNCHRONOUS SEQUENTIAL CIRCUITS; PARTIAL-SCAN DELAY FAULT TESTING;

SEQUENTIAL CIRCUITS;

EID: 0032205486     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736191     Document Type: Article

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