Delay-insensitive multi-ring structures

Integration, the VLSI Journal

Volumn 15, Issue 3, 1993, Pages 313-340

  Sparsø, Jens ^a   Staunstrup, Jørgen ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

Delay insensitive circuits; performance analysis; self timed circuits; vector multiplier; VLSI design

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; DIGITAL FILTERS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MULTIPLYING CIRCUITS; PERFORMANCE; TIMING CIRCUITS; VECTORS;

DELAY INSENSITIVE CIRCUITS; SELF TIMED CIRCUITS; VECTOR MULTIPLIER;

VLSI CIRCUITS;

EID: 0027677633     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9260(93)90035-B     Document Type: Article

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