Testing asynchronous circuits: A survey

Integration, the VLSI Journal

Volumn 19, Issue 3, 1995, Pages 111-131

  Hulgaard, Henrik ^a   Burns, Steven M ^a   Borriello, Gaetano ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Asynchronous circuits; Path delay fault testing; Self checking circuits; Stuck at fault testing; Test generation

Indexed keywords

FABRICATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

ASYNCHRONOUS CIRCUITS; PATH DELAY FAULT TESTING; SELF CHECKING CIRCUITS; STUCK AT FAULT TESTING; TEST GENERATION;

LOGIC CIRCUITS;

EID: 0029404469     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9260(95)00012-5     Document Type: Article

References (43)

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