On the design of path delay fault testable combinational circuits

Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)

Volumn , Issue , 1990, Pages 374-381

  Pramanick, Ankan K ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS--SYNTHESIS;

EXTENDED FACTORIZATION; MULTILEVEL LOGIC CIRCUITS; PATH DELAY FAULT TESTABILITY;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0025658543     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)