Synthesis of Robust Delay-Fault-Testable Circuits: Theory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 1, 1992, Pages 87-101

  Devadas, Srinivas ^a   Keutzer, Kurt ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL--DESIGN;

DELAY-FAULT-TESTABLE CIRCUITS; DESIGN FOR TESTABILITY;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0026679188     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.108622     Document Type: Article

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