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Volumn 39, Issue 12, 1990, Pages 1456-1463

A Simulation-Based Method for Generating Tests for Sequential Circuits

Author keywords

Automatic testing; digital circuits; sequential circuits; simulation; test generation

Indexed keywords

COMPUTER SIMULATION - APPLICATIONS; LOGIC CIRCUITS, SEQUENTIAL - TESTING; SWITCHING THEORY - SEQUENTIAL SWITCHING;

EID: 0025638084     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.61065     Document Type: Article
Times cited : (5)

References (10)
  • 1
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    • A simulation-based directed-search method for test generation
    • (ICCD’87), Port Chester, NY, Oct.
    • K. T. Cheng and V. D. Agrawal, “A simulation-based directed-search method for test generation,” in Proc. Int. Conf. Comput. Design (ICCD’87), Port Chester, NY, Oct. 1987, pp. 48–51.
    • (1987) Proc. Int. Conf. Comput. Design , pp. 48-51
    • Cheng, K.T.1    Agrawal, V.D.2
  • 2
    • 84911547644 scopus 로고
    • Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits
    • Oct.
    • J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,” IEEE Trans. Electron. Comput., vol. EC-16, pp. 567–580, Oct. 1967.
    • (1967) IEEE Trans. Electron. Comput. , vol.EC-16 , pp. 567-580
    • Roth, J.P.1    Bouricius, W.G.2    Schneider, P.R.3
  • 3
    • 0019543877 scopus 로고
    • An implicit enumeration algorithm to generate tests for combinational logic circuits
    • Mar.
    • P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. Comput., vol. C-30, pp. 215–222, Mar. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 215-222
    • Goel, P.1
  • 4
    • 33746935415 scopus 로고
    • A procedure for generating test sequences to detect sequential circuit failures
    • Oct.
    • H. Kubo, “A procedure for generating test sequences to detect sequential circuit failures,” NEC J. Res. Develop., vol. 12, pp. 69–78, Oct. 1968.
    • (1968) NEC J. Res. Develop. , vol.12 , pp. 69-78
    • Kubo, H.1
  • 5
    • 0016961573 scopus 로고
    • A nine-value circuit model for test generation
    • June
    • P. Muth, “A nine-value circuit model for test generation,” IEEE Trans. Comput., vol. C-25, pp. 630–636, June 1976.
    • (1976) IEEE Trans. Comput. , vol.C-25 , pp. 630-636
    • Muth, P.1
  • 6
    • 0017417099 scopus 로고
    • Simulator oriented fault test generator
    • New Orleans, LA, June
    • T. J. Snethen, “Simulator oriented fault test generator,” in Proc. 14th Design Automat. Conf., New Orleans, LA, June 1977, pp. 88–93.
    • (1977) Proc. 14th Design Automat. Conf. , pp. 88-93
    • Snethen, T.J.1
  • 7
    • 0022037569 scopus 로고
    • Test generation by activation and defect drive (TEGAD)
    • Mar.
    • S. Nitta, K. Kawamura, and K. Hirabayashi, “Test generation by activation and defect drive (TEGAD),” Integration, VLSI J., vol. 3, pp. 3–12, Mar. 1985.
    • (1985) Integration, VLSI J. , vol.3 , pp. 3-12
    • Nitta, S.1    Kawamura, K.2    Hirabayashi, K.3
  • 8
    • 0142046626 scopus 로고
    • Concurrent simulation of nearly identical digital networks
    • Apr.
    • E. G. Ulrich and T. Baker, “Concurrent simulation of nearly identical digital networks,” IEEE Comput. Mag., vol. 7, pp. 39–44, Apr. 1974.
    • (1974) IEEE Comput. Mag. , vol.7 , pp. 39-44
    • Ulrich, E.G.1    Baker, T.2
  • 10
    • 0022305007 scopus 로고
    • A sequential circuit test generation system
    • Philadelphia, PA, Nov.
    • S. Mallela and S. Wu, “A sequential circuit test generation system,” in Proc. Int. Test Conf., Philadelphia, PA, Nov. 1985, pp. 57–61.
    • (1985) Proc. Int. Test Conf. , pp. 57-61
    • Mallela, S.1    Wu, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.