Synthesis for Testability Techniques for Asynchronous Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 12, 1995, Pages 1569-1577

  Sangiovanni Vincentelli, Alberto ^c  

^a SYNOPSYS INC   (United States)

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC NETWORK SYNTHESIS; FAILURE ANALYSIS; GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL MODELS; OPTIMIZATION; SEQUENTIAL CIRCUITS; SET THEORY;

ASYNCHRONOUS CIRCUITS; HAZARD FREE ROBUST PATH DELAY FAULT TESTABILITY; SIGNAL TRANSITION GRAPH;

LOGIC DESIGN;

EID: 0029547054     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.476586     Document Type: Article

References (20)

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