Sequential circuit fault simulation using logic emulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 8, 1998, Pages 724-736

  Hwang, Shih Arn ^a   Hong, Jin Hua ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

CLB; Fault emulation; Fault injection; Fault simulation; FPGA; Logic emulation; Logic testing

Indexed keywords

COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; SEQUENTIAL CIRCUITS;

FAULT EMULATION; FAULT INJECTION; LOGIC EMULATION;

LOGIC DESIGN;

EID: 0032137021     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.712103     Document Type: Article

References (28)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
2. N. Gouders and R. Kaibel, "PARIS: A parallel pattern fault simulato for synchronous sequential circuits," in Proc. IEEE Int. Conf. Computer Aided Design (ICCAD), 1991, pp. 542-545.
3. C.-P. Kung and C.-S. Lin, "Parallel sequence fault simulation fo synchronous sequential circuits," in Proc. European Design Automatio Conference (EDAC). 1992, pp. 434-438.
4. T. M. Niermann, W.-T. Cheng, and J. H. Patel, "PROOFS: A fast, memory efficient sequential circuit fault simulator," IEEE Trans. Computer Aided Design, vol. 11, pp. 198-207, Feb. 1992.
5. O. Y. Song and P. R. Menon, "3-valued trace-based fault simulation o synchronous sequential circuits," IEEE Trans. Computer-Aided Design vol. 12, pp. 1419-1424, Sept. 1993.
6. C. R. Graham, E. M. Rudnick, and J. H. Patel, "Dynamic fault groupin for PROOFS: A win for large sequential circuits," in Proc. Int. Conf VLSI Design, Jan. 1997, pp. 495-501.
7. H.-K. Lee and D.-S. Ha, "HOPE: An efficient parallel fault simula- tor for synchronous sequential circuits," in Proc. IEEE/ACM Desig Automation Conf. (DAC), 1992, pp. 336-340.
8. "New methods of improving parallel fault simulation in synchronous sequential circuits," in Proc. IEEE Int. Conf. Computer-Aide Design (ICCAD), 1993, pp. 10-17.
9. C.-P. Kung and C.-S. Lin, "HyHOPE: A fast fault simulator wit efficient simulation of hypertrophie faults," in Proc. IEEE Int. Conf Computer-Aided Design (ICCAD), 1994, pp. 714-718.
10. T. Markas, M. Royals, and N. Kanopoulos, "On distributed faul simulation," IEEE Computer, vol. 23, pp. 40-52, Jan. 1990.
11. P. A. Duba, R. K. Roy, J. A. Abraham, and W. A. Rogers, "Faul simulation in a distributed environment," in Proc. IEEE/ACM Desig Automation Conf. (DAC), 1988, pp. 686-691.
12. S. Parkes, P. Banerjee, and J. Patel, "A parallel algorithm for faul simulation based on PROOFS," in Proc. Int. Conf. Computer Desig (ICCD), 1995, pp. 616-621.
13. M. B. Amin and B. Vinnakota, "ZAMBEZI: A parallel pattern paralle fault sequential circuit fault simulator," in Proc. IEEE VLSI Test Symp (VTS), 1996, pp. 438-443.
14. "Zamlog: A parallel algorithm for fault simulation based o Zambezi," in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD) 1996, pp. 509-512.
15. E. M. Rudnick and J. H. Patel, "Overcoming the serial logic simulatio bottleneck in parallel fault simulation," in Proc. Int. Conf. VLSI Design Jan. 1997, pp. 542-544.
16. D. Krishnaswamy, E. M. Rudnick, J. H. Patel, and P. Banerjee "SPITFIRE: Scalable parallel algorithms for test set partitioned faul simulation," in Proc. IEEE VLSI Test Symp. (VTS), Apr. 1997, pp 274-281.
17. S. Walters, "Computer-aided prototyping for ASIC-based systems, IEEE Design Test Comput., vol. 8, pp. 4-10, 1991.
18. J. Varghese, M. Butts, and J. Batcheller, "An efficient logic emulatio system," IEEE Trans. VLSI Syst., vol. 1, pp. 171-174, June 1993.
19. J. Dunlop, D. Girma, and P. Lysaght, "Alternative approach to ASI design methodology based on reconfigurable logic devices," Proc. Inst Elect. Eng., vol. 139, pt. G, pp. 217-221, Apr. 1992.
20. S. M. Trimberger, "A reprogrammable gate array and applications, Proc. IEEE, vol. 81, pp. 1030-1041, July 1993.
21. Y.-L. Li and C.-W. Wu, "Cellular automata for efficient parallel logi and fault simulation," IEEE Trans. Computer-Aided Design, vol. 14, pp 740-749, June 1995.
22. Y.-L. Li, Y.-C. Lai, and C.-W. Wu, "VLSI design of a cellular-automat based logic and fault simulator," Proc. Nat. Sci. Council Part A: Phys Sci. Eng., vol. 21, pp. 189-199, May 1997.
23. Xilinx, The Programmable Gate Array Data Book, Xilinx, Inc., Sa Jose, CA, 1996.
24. K.-T. Cheng, S.-Y. Huang, and W.-J. Dai, "Fault emulation: A ne approach to fault grading," in Proc. IEEE Int. Conf. Computer-Aide Design (ICCAD), 1995, pp. 681-686.
25. L. Burgun, F. Reblewski, G. Fenelon, J. Bariber, and O. Lepape, "Seria fault emulation," in Proc. IEEE/ACM Design Automation Conf. (DAC) Las Vegas, NV, June 1996, pp. 801-806.
26. J.-H. Hong, S.-A. Hwang, and C.-W. Wu, "An FPGA-based hardwar emulator for fast fault emulation," in Proc. Midwest Symp. Circuits Syst. Ames, IA, Aug. 1996.
27. V. S. lyengar and D. T. Tang, "On simulating faults in parallel," i Proc. Int. Symp. Fault Tolerant Computing (FTCS), 1988, pp. 110-115.
28. M. Abramovici, P. R. Menon, and D. T. Miller, "Critical path tracing-An alternative to fault simulation," in Proc. IEEE/ACM Desig Automation Conf. (DAC), 1983, pp. 214-220.