An Efficient Logic Emulation System

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 2, 1993, Pages 171-174

  Varghese, Joseph ^a   Butts, Michael ^a   Batcheller, Jon ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS; INTERCONNECTS; LOGIC EMULATOR;

LOGIC CIRCUITS;

EID: 0027614653     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.238418     Document Type: Article

References (9)

1. M. Butts and J. Batcheller, “Method of using electronically reconfigurable logic circuits,” U.S. Patent 5 036 473, July 30, 1991.
2. M. Butts, J. Batcheller and J. Varghese, “An efficient logic emulation system,” in Proc. Int. Conf. on Computer Design, pp. 138–141, Oct. 1992.
3. Xilinx, Inc., The Programmable Gate Array Data Book, Xilinx, San Jose, 1992.
4. S. Walters, “Computer-aided prototyping for ASIC-based systems,” IEEE Design & Test, pp. 4–10, June 1991.
5. G. Masson, G. Gingher, and S. Nakamura, “A sampler of circuit switching networks,” IEEE Computer, pp. 32–48, June 1979.
6. L. Maliniak, “Multiplexing enhances hardware emulation,” Electronic Design, pp. 76–78, Nov. 1992.
7. M. Butts, J. Batcheller, and M. Heising, “Programmable interconnect for logic emulation,” Quickturn Systems, Oct. 1992, (in review).
8. C. Cox and W. Blanz, “Ganglion—A fast hardware implementation of a connectionist classifier,” in Proc. IEEE Custom Integrated Circuits Conf., 1991.
9. M. Shand, P. Bertin, and J. Vuillemin, “Hardware speedups in long integer multiplication,” ACM Computer Architecture News, pp. 106–113, Mar. 1991.