PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 2, 1992, Pages 198-207

  Niermann, Thomas M ^a   Cheng, Wu Tung ^a   Patel, Janak H ^b  

^a Sunrise Test Systems ^*  (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; COMPUTER SIMULATION--APPLICATIONS;

MEMORY-EFFCIENT SEQUENTIAL CIRCUIT FAULT SIMULATOR; PROOFS ALGORITHM; PROOFS FAULT SIMULATOR; SINGLE FAULT SIMULATION; SYNCHRONOUS SEQUENTIAL CIRCUITS;

AUTOMATA THEORY;

EID: 0026819183     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.124398     Document Type: Article

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