Parallel algorithm for fault simulation based on PROOFS

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1995, Pages 616-621

  Parkes, Steven ^a   Banerjee, Prithviraj ^a   Patel, Janak ^a  

^a Vista Research Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; FAILURE ANALYSIS; OBJECT ORIENTED PROGRAMMING; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; SEQUENTIAL CIRCUITS; SUBROUTINES;

DISTRIBUTED MEMORY; FAULT PARTITIONING; FAULT REDISTRIBUTION; FAULT SIMULATION; FAULT SIMULATION PACKAGE; HYBRID ARCHITECTURE; LIBRARY; PARALLELISM; SHARED MEMORY;

COMPUTER SIMULATION;

EID: 0029503179     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)