Computer-Aided Prototyping for ASIC-Based Systems

IEEE Design and Test of Computers

Volumn 8, Issue 2, 1991, Pages 4-10

  Walters, Stephen ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; MICROPROCESSOR CHIPS - COMPUTER AIDED DESIGN;

ASIC-BASED SYSTEMS DESIGN; COMPUTER AIDED PROTOTYPING; EMULATION HARDWARE; REPROGRAMMABLE HARDWARE; RPM EMULATION SYSTEM; SILICON PROTOTYPING;

INTEGRATED CIRCUITS;

EID: 0026173694     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.82034     Document Type: Article

References (5)

1. The Programmable Gate Array Data Book, Xilinx, San Jose, Calif., 1991.
2. B. Preas and P. Karger, “Placement, Assignment, and Floorplanning,” in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti eds., Benjamin/Cummings Pub., Menlo Park, Calif., 1988, pp.87–155.
3. Electronic Design Interchange Format Version 2.0.0, EIA/EDIF/IS-44, Electronic Industries Assoc., Washington, D.C., May 1987.
4. D.Gajeski and Y.Lin, “Module Generation and Silicon Compilation,” in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti, eds., Benjamin/Cummings Pub., Menlo Park, Calif., 1988, pp. 283–345.
5. M. Lorenzetti and D. Baeder, “Routing,” in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti, eds., Benjamin/Cummings Pub., Menlo Park, Calif., 1988, pp. 157–210.