Overcoming the serial logic simulation bottleneck in parallel fault simulation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1997, Pages 495-501

  Rudnick, E M ^a   Patel, J H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FORMAL LOGIC; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

FAULT SIMULATION;

COMPUTER AIDED DESIGN;

EID: 0030737338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)