ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 438-443

  Amin, Minesh B ^a   Vinnakota, Bapiraju ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; LOGIC GATES; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; VECTORS;

BENCHMARK CIRCUITS; COMPUTER DATA WORD; MULTIPLE FAULTS; PARALLEL PATTERN PARALLEL FAULT SIMULATION; SEQUENTIAL CIRCUIT FAULT SIMULATORS;

SEQUENTIAL CIRCUITS;

EID: 0029709607     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)