Dynamic fault grouping for PROOFS: a win for large sequential circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1997, Pages 542-544

  Graham, C R ^a   Rudnick, E M ^a   Patel, J H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FLIP FLOP CIRCUITS; PARALLEL PROCESSING SYSTEMS; SIMULATORS; VLSI CIRCUITS;

FAULT GROUPING;

SEQUENTIAL CIRCUITS;

EID: 0030837857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)