-
1
-
-
0027242437
-
"A high-speed 0.6-//m 16K CMOS gâte array on a thin SIMOX film,"
-
vol. 40, p. 179, Jan. 1993.
-
Y. Yamaguchi, A. Ishibashi, M. Shimizu, T. Nishimura, K. Tsukamoto, K. Horie, and Y. Akasaka, "A high-speed 0.6-//m 16K CMOS gâte array on a thin SIMOX film," IEEE Trans. Electron Devices, vol. 40, p. 179, Jan. 1993.
-
IEEE Trans. Electron Devices
-
-
Yamaguchi, Y.1
Ishibashi, A.2
Shimizu, M.3
Nishimura, T.4
Tsukamoto, K.5
Horie, K.6
Akasaka, Y.7
-
2
-
-
0029482709
-
"A high performance 16M DRAM on a thin film SOI,"
-
143, 1995.
-
H. S. Kim, S. B. Lee, D. U. Choi, J. H. Shin, K. C. Lee, K. P. Lee, K. N. Kim, and J. W. Park, "A high performance 16M DRAM on a thin film SOI," VLSI Tech. Dig., p. 143, 1995.
-
VLSI Tech. Dig., P.
-
-
Kim, H.S.1
Lee, S.B.2
Choi, D.U.3
Shin, J.H.4
Lee, K.C.5
Lee, K.P.6
Kim, K.N.7
Park, J.W.8
-
3
-
-
33747443321
-
"TFSOI CMOS technology for sub-IV microcontroller circuits," in
-
1995, p. 59.
-
W. M. Huang, K. Papworth, M. Racanelli, J. Foerstner, H. C. Chin, H. Park, B. Y. Hwang, T, Wetteroth, S. Hong, H. Shin, S. Wilson, and S. Cheng, "TFSOI CMOS technology for sub-IV microcontroller circuits," in IEDM Tech. Dig., 1995, p. 59.
-
IEDM Tech. Dig.
-
-
Huang, W.M.1
Papworth, K.2
Racanelli, M.3
Foerstner, J.4
Chin, H.C.5
Park, H.6
Hwang, B.Y.7
Wetteroth8
Hong, S.9
Shin, H.10
Wilson, S.11
Cheng, S.12
-
4
-
-
0029491760
-
"Substantial advantages of fully-depleted CMOS/SIMOX devices as low-power high-performance VLSI components compared with its bulk-CMOS counterpart," in
-
1995, p. 635.
-
Y. Kado, H. Inokawa, Y. Okazaki, T. Tsuchiya, Y. Kawai, M. Sato, Y. Sakakibara, S. Nakayama, H. Yamada, M. Kitamura, S. Nakashima, K. Nishimura, S. Date, M. Ino, K. Takeya, and T. Sakai, "Substantial advantages of fully-depleted CMOS/SIMOX devices as low-power high-performance VLSI components compared with its bulk-CMOS counterpart," in IEDM Tech. Dig., 1995, p. 635.
-
IEDM Tech. Dig.
-
-
Kado, Y.1
Inokawa, H.2
Okazaki, Y.3
Tsuchiya, T.4
Kawai, Y.5
Sato, M.6
Sakakibara, Y.7
Nakayama, S.8
Yamada, H.9
Kitamura, M.10
Nakashima, S.11
Nishimura, K.12
Date, S.13
Ino, M.14
Takeya, K.15
Sakai, T.16
-
5
-
-
0031069052
-
"A 40 Gb/s 8x8 ATM switch LSI using 0.25 //m CMOS/SIMOX," in
-
1997, p. 154.
-
Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, "A 40 Gb/s 8x8 ATM switch LSI using 0.25 //m CMOS/SIMOX," in ISSCC Dig. Tech. Papers, 1997, p. 154.
-
ISSCC Dig. Tech. Papers
-
-
Ohtomo, Y.1
Yasuda, S.2
Nogawa, M.3
Inoue, J.4
Yamakoshi, K.5
Sawada, H.6
Ino, M.7
Hino, S.8
Sato, Y.9
Takei, Y.10
Watanabe, T.11
Takeya, K.12
-
6
-
-
0028735418
-
"Dynamic floating-body instabilities in partially depleted SOI CMOS circuits," in 1EDM
-
1994, p. 661.
-
D. Suh and J. G. Possum, "Dynamic floating-body instabilities in partially depleted SOI CMOS circuits," in 1EDM Tech. Dig., 1994, p. 661.
-
Tech. Dig.
-
-
Suh, D.1
Possum, J.G.2
-
7
-
-
0029287689
-
"A physical charge-based model for nonfully depleted SOI MOSFET's and its use in assessing floating-body effects in SOI CMOS circuits,"
-
vol. 42, p. 728, Apr. 1995.
-
"A physical charge-based model for nonfully depleted SOI MOSFET's and its use in assessing floating-body effects in SOI CMOS circuits," IEEE Trans. Electron Devices, vol. 42, p. 728, Apr. 1995.
-
IEEE Trans. Electron Devices
-
-
-
8
-
-
0029492926
-
"A study of floating-body effects on inverter chain delay," in
-
1995, p. 125.
-
R. A. Schiebel, T. W. Houston, R. Rajgopal, and K. Joyner, "A study of floating-body effects on inverter chain delay," in IEEE Int. SOI Conf., 1995, p. 125.
-
IEEE Int. SOI Conf.
-
-
Schiebel, R.A.1
Houston, T.W.2
Rajgopal, R.3
Joyner, K.4
-
9
-
-
0029713421
-
"History dependence of nonfully depleted (NFD) digital SOI circuits," in
-
1996, p. 122.
-
F. Assaderaghi, G. G. Shahidi, M. Hargrove, K. Hathorn, H. Hovel, S. Kulkarni, W. Rausch, D. Sadana, D. Schepis, R. Schulz, D. Yee, J. Sun, R. Dennard, and B. Davari, "History dependence of nonfully depleted (NFD) digital SOI circuits," in Symp. VLSI Technol., 1996, p. 122.
-
Symp. VLSI Technol.
-
-
Assaderaghi, F.1
Shahidi, G.G.2
Hargrove, M.3
Hathorn, K.4
Hovel, H.5
Kulkarni, S.6
Rausch, W.7
Sadana, D.8
Schepis, D.9
Schulz, R.10
Yee, D.11
Sun, J.12
Dennard, R.13
Davari, B.14
-
10
-
-
0000913824
-
"Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology," in
-
1994, p. 401.
-
T. Tsuchiya, T. Ohno, and Y. Kado, "Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology," in Proc. Symp. SOI Tech. and Devices, Electrochem. Soc., 1994, p. 401.
-
Proc. Symp. SOI Tech. and Devices, Electrochem. Soc.
-
-
Tsuchiya, T.1
Ohno, T.2
Kado, Y.3
-
11
-
-
0029406028
-
"Transient behavior of the kink effect in partially depleted SOI MOSFET's,"
-
vol. 16, p. 494, Nov. 1995.
-
A. Wei, M. J. Sherony, and D. A. Antoniadis, "Transient behavior of the kink effect in partially depleted SOI MOSFET's," IEEE Electron Device Lett., vol. 16, p. 494, Nov. 1995.
-
IEEE Electron Device Lett.
-
-
Wei, A.1
Sherony, M.J.2
Antoniadis, D.A.3
-
12
-
-
0029409871
-
"On the transient operation of partially depleted SOI MOSFET's,"
-
16, p. 497, Nov. 1995.
-
J. Gautier and J. Y. C. Sun, "On the transient operation of partially depleted SOI MOSFET's," IEEE Electron Device Lett., vol. EDE-16, p. 497, Nov. 1995.
-
IEEE Electron Device Lett., Vol. EDE
-
-
Gautier, J.1
Sun, J.Y.C.2
-
13
-
-
0029753842
-
"History dependence of output characteristics of silicon-on-insulator (SOI) MOSFET's,"
-
vol. 17, p. 7, Jan. 1996.
-
K. A. Jenkins, J. Y. C. Sun, and J. Gautier, "History dependence of output characteristics of silicon-on-insulator (SOI) MOSFET's," IEEE Electron Device Lett., vol. 17, p. 7, Jan. 1996.
-
IEEE Electron Device Lett.
-
-
Jenkins, K.A.1
Sun, J.Y.C.2
Gautier, J.3
-
14
-
-
0030080724
-
"Analysis of floating body induced transient behaviors in partially depleted thin film SOI devices,"
-
vol. 43, p. 318, Feb. 1996.
-
H. C. Shin, I. S. Eim, M. Racanelli, W. E. M. Huang, J. Foerstner, and B.-Y. Hwang, "Analysis of floating body induced transient behaviors in partially depleted thin film SOI devices," IEEE Trans. Electron Devices, vol. 43, p. 318, Feb. 1996.
-
IEEE Trans. Electron Devices
-
-
Shin, H.C.1
Eim, I.S.2
Racanelli, M.3
Huang, W.E.M.4
Foerstner, J.5
Hwang, B.-Y.6
-
15
-
-
0030151464
-
"Eow-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's,"
-
vol. 17, p. 196, May 1996.
-
M. M. Pelella, J. G. Possum, D. Suh, S. Krishnan, K. A. Jenkins, and M. J. Hargrove, "Eow-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's," IEEE Electron Device Lett., vol. 17, p. 196, May 1996.
-
IEEE Electron Device Lett.
-
-
Pelella, M.M.1
Possum, J.G.2
Suh, D.3
Krishnan, S.4
Jenkins, K.A.5
Hargrove, M.J.6
-
16
-
-
0030388127
-
"Effect of body-charge on fully and partially depleted SOI MOSFET design," in
-
1996, p. 125.
-
M. J. Sherony, A. Wei, and D. A. Antoniadis, "Effect of body-charge on fully and partially depleted SOI MOSFET design," in IEDM Tech. Dig., 1996, p. 125.
-
IEDM Tech. Dig.
-
-
Sherony, M.J.1
Wei, A.2
Antoniadis, D.A.3
-
17
-
-
0029481651
-
"Eeakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM," in
-
1995, p. 141.
-
F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, "Eeakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM," in Symp. VLSI Technol., 1995, p. 141.
-
Symp. VLSI Technol.
-
-
Morishita, F.1
Suma, K.2
Hirose, M.3
Tsuruda, T.4
Yamaguchi, Y.5
Eimori, T.6
Oashi, T.7
Arimoto, K.8
Inoue, Y.9
Nishimura, T.10
-
18
-
-
0030150564
-
"Measurement of transient effects in SOI DRAM/SRAM access transistors,"
-
vol. 17, p. 193, May 1996.
-
A. Wei and D. A. Antiniadis, "Measurement of transient effects in SOI DRAM/SRAM access transistors," IEEE Electron Device Lett., vol. 17, p. 193, May 1996.
-
IEEE Electron Device Lett.
-
-
Wei, A.1
Antiniadis, D.A.2
-
19
-
-
33747388525
-
"Transient effects of SOI transistors in circuit operation," in
-
1996, vol. 96-1, p. 548 or vol. 96-3, p. 397.
-
I. J. Kim, H. O. Joachim, T. Iwamatsu, Y. Yamaguchi, Y. Inoue, K. Eikyu, K. Ishikawa, K. Ueda, H. Morinaka, K. Mashiko, and H. Miyoshi, "Transient effects of SOI transistors in circuit operation," in Proc. Electrochem. Soc. Spring Meet., 1996, vol. 96-1, p. 548 or vol. 96-3, p. 397.
-
Proc. Electrochem. Soc. Spring Meet.
-
-
Kim, I.J.1
Joachim, H.O.2
Iwamatsu, T.3
Yamaguchi, Y.4
Inoue, Y.5
Eikyu, K.6
Ishikawa, K.7
Ueda, K.8
Morinaka, H.9
Mashiko, K.10
Miyoshi, H.11
-
20
-
-
0030393799
-
"Suppression of delay time instability on frequency using field shield isolation technology for deep submicron SOI circuits," in
-
1996, p. 129.
-
S. Maeda, Y. Yamaguchi, I. J. Kim, T. Iwamatsu, T. Ipposhi, S. Miyamoto, S. Maegawa, K. Ueda, K. Nil, K. Mashiko, Y. Inoue, and H. Miyoshi, "Suppression of delay time instability on frequency using field shield isolation technology for deep submicron SOI circuits," in IEDM Tech. Dig., 1996, p. 129.
-
IEDM Tech. Dig.
-
-
Maeda, S.1
Yamaguchi, Y.2
Kim, I.J.3
Iwamatsu, T.4
Ipposhi, T.5
Miyamoto, S.6
Maegawa, S.7
Ueda, K.8
Nil, K.9
Mashiko, K.10
Inoue, Y.11
Miyoshi, H.12
-
21
-
-
0029723460
-
"Suppression of the SOI floating-body effects by linked-body device structure," in
-
1996, p. 92.
-
W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, "Suppression of the SOI floating-body effects by linked-body device structure," in Symp. VLSI Techol, 1996, p. 92.
-
Symp. VLSI Techol
-
-
Chen, W.1
Taur, Y.2
Sadana, D.3
Jenkins, K.A.4
Sun, J.5
Cohen, S.6
-
22
-
-
0027813431
-
"CAD-compatible high-speed CMOS/SIMOX technology using fieldshield isolation for im gate array," in
-
1993, p. 475.
-
T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, "CAD-compatible high-speed CMOS/SIMOX technology using fieldshield isolation for IM gate array," in IEDM Tech. Dig., 1993, p. 475.
-
IEDM Tech. Dig.
-
-
Iwamatsu, T.1
Yamaguchi, Y.2
Inoue, Y.3
Nishimura, T.4
Tsubouchi, N.5
-
23
-
-
33747433555
-
"High-speed 0.5-ftm SOI 1/8 frequency divider with body-fixed structure for wide range of applications," in
-
575, 1995.
-
T. Iwamatsu, Y. Yamaguchi, K. Ueda, K. Mashiko, Y. Inoue, and T. Hirao, "High-speed 0.5-ftm SOI 1/8 frequency divider with body-fixed structure for wide range of applications," in Ext. Abst. SSDM, p. 575, 1995.
-
Ext. Abst. SSDM, P.
-
-
Iwamatsu, T.1
Yamaguchi, Y.2
Ueda, K.3
Mashiko, K.4
Inoue, Y.5
Hirao, T.6
-
24
-
-
0029406076
-
"CAD-compatible high-speed CMOS/SIMOX gate array using fieldshield isolation,"
-
42, p. 1934, Nov. 1995.
-
T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, "CAD-compatible high-speed CMOS/SIMOX gate array using fieldshield isolation," IEEE Trans. Electron Devices, vol. ED-42, p. 1934, Nov. 1995.
-
IEEE Trans. Electron Devices, Vol. ED
-
-
Iwamatsu, T.1
Yamaguchi, Y.2
Inoue, Y.3
Nishimura, T.4
Tsubouchi, N.5
-
25
-
-
0031074275
-
"A CADcompatible SOI/CMOS gate array having body-fixed partially-depleted transistors,"
-
1997, p. 288.
-
K. Ueda, K. Nii, Y. Wada, I. Takimoto, S. Maeda, T. Iwamatsu, Y. Yamaguchi, S. Maegawa, K. Mashiko, and H. Hamano, "A CADcompatible SOI/CMOS gate array having body-fixed partially-depleted transistors," ISSCC Dig. Tech. Papers, 1997, p. 288.
-
ISSCC Dig. Tech. Papers
-
-
Ueda, K.1
Nii, K.2
Wada, Y.3
Takimoto, I.4
Maeda, S.5
Iwamatsu, T.6
Yamaguchi, Y.7
Maegawa, S.8
Mashiko, K.9
Hamano, H.10
-
26
-
-
0030699855
-
"A highly reliable 0.35-ftm field shield body-tied SOI gate array for substrate-bias-effect free operation," in
-
1997, p. 93.
-
S. Maeda, Y. Yamaguchi, I. J. Kim, T. Iwamatsu, T. Ipposhi, S. Miyamoto, Y. Hirano, K. Ueda, K. Nii, K. Mashiko, S. Maegawa, Y. Inoue, and T. Nishimura, "A highly reliable 0.35-ftm field shield body-tied SOI gate array for substrate-bias-effect free operation," in Symp. VLSI Technol, 1997, p. 93.
-
Symp. VLSI Technol
-
-
Maeda, S.1
Yamaguchi, Y.2
Kim, I.J.3
Iwamatsu, T.4
Ipposhi, T.5
Miyamoto, S.6
Hirano, Y.7
Ueda, K.8
Nii, K.9
Mashiko, K.10
Maegawa, S.11
Inoue, Y.12
Nishimura, T.13
-
28
-
-
0031366647
-
"A method for the prediction of hot-carrier lifetime in floating SOI NMOSFET's,"
-
vol. 44, p. 2200, Dec. 1997.
-
S. Maeda, Y. Yamaguchi, I. J. Kirn, H. O. Joachin, Y. Inoue, H. Miyoshi, and A. Yasuoka, "A method for the prediction of hot-carrier lifetime in floating SOI NMOSFET's," IEEE Trans. Electron Devices, vol. 44, p. 2200, Dec. 1997.
-
IEEE Trans. Electron Devices
-
-
Maeda, S.1
Yamaguchi, Y.2
Kirn, I.J.3
Joachin, H.O.4
Inoue, Y.5
Miyoshi, H.6
Yasuoka, A.7
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