Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's

IEEE Electron Device Letters

Volumn 17, Issue 5, 1996, Pages 196-198

  Pelella, Mario M ^a,b   Fossum, Jerry G ^a,c   Suh, Dongwook ^c   Krishnan, Srinath ^c   Jenkins, Keith A ^d   Hargrove, Michael J ^b  

^a IEEE

^b IBM MICROELECTRONICS   (United States)

^c University of Florida   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; DIGITAL CIRCUITS; ELECTRIC BREAKDOWN; ELECTRIC CHARGE; ELECTRIC CURRENTS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC VARIABLES MEASUREMENT; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; TRANSIENTS;

PASS TRANSISTORS; PULSE MEASUREMENT; SCALED FLOATING BODY; TRANSIENT EFFECT;

MOSFET DEVICES;

EID: 0030151464     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.491827     Document Type: Article

References (8)

1. G. G. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chappell, J. H. Comfort, B. Deveri, R. H. Dennard, R. L. Franch, P. A. McFarland, J. S. Neely, T. H. Ning, M. R. Polcari, and J. D. Warnock, "A room temperature 0.1 μm CMOS on SOI," IEEE Trans, Electron Devices, vol. 41, p. 2405, Dec. 1994.
2. D. Suh and J. G. Fossum, "Dynamic Floating-body instabilities in partially depleted SOI SMOS circuits," IEEE IEDM Tech. Dig., p. 661, Dec. 1994.
3. C. Leroux, J. Gautier, A. J. Auberton-Herve, B. Giffard, and M. Spalanzani, "Parasitic transients induced by floating substrate effect and bipolar transistor on SOI technologies," Microelectron. Eng., vol. 15, p. 199, 1991.
4. M. M. Pelella, J. G. Fossum, D. Suh, S. Krishnan, and K. A. Jenkins, "Low-voltage transient bipolxr effect induced by dynamic floating-body charging in PD/SOI MOSFET'S" in Proc. IEEE Int. SOI Conf., Oct. 1995, p. 8.
5. H. K. Lim and J. G. Fossum, "Transient drain current and propagation delay in SOI CMOS," IEEE Trans, Electron Devices, vol. ED-31, p. 1251, Sept. 1984.
6. D. Suh and J. G. Fossum, "A physical charge-based model for nonfully depleted SOI MOSFET'S and its use in assessing floating-body effects in SOI CMOS circuits," IEEE Trans. Electron Devices, vol. 42, p. 728, Apr. 1995.
7. M. Yashimi, M. Terauchi, A. Murakoshi, M. Takahashi, K. Matsuzawa, N. Shigyo, and Y. Ushiku, "Technology trends of silicon-on-insulator - Its advantages and problems to be solved," IEEE IEDM Tech. Dig., P. 429, Dec. 1994.
8. K. A. Jenkins and J. Y.-C. Sun, "Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heatong," IEEE Electron Device Lett., vol. 16, p. 145, Apr. 1995.