Highly reliable 0.35 μm field-shield body-tied SOI gate array for substrate-bias-effect free operation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 93-94

  Maeda, S ^a   Yamaguchi, Y ^a   Kim, I J ^a   Iwamatsu, T ^a   Ipposhi, T ^a   Miyamoto, S ^a   Hirano, Y ^a   Ueda, K ^a   Nii, K ^a   Mashiko, K ^a   Maegawa, S ^a   Inoue, Y ^a   Nishimura, T ^a  

^a ULSI Lab   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC BREAKDOWN OF SOLIDS; GATES (TRANSISTOR); OXIDES; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; VOLTAGE MEASUREMENT;

FIELD SHIELD (FS) SILICON ON INSULATOR GATE (SOI); FLOATING BODY EFFECTS;

MOSFET DEVICES;

EID: 0030699855     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)