Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's

IEEE Transactions on Electron Devices

Volumn 45, Issue 6, 1998, Pages 1310-1316

  Biesemans, Serge ^a,b   Hendriks, Marton ^a   Kubicek, Stefan ^a   De Meyer, Kristin ^a  

^a IMEC   (Belgium)

^b NONE

Author keywords

Effective channel length; Series resistance

Indexed keywords

ELECTRIC RESISTANCE; ERROR ANALYSIS; MICROELECTRONICS; PROCESS CONTROL; STATISTICAL METHODS;

EFFECTIVE CHANNEL LENGTH; RESISTANCE EXTRACTION METHODS;

MOSFET DEVICES;

EID: 0032099279     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.678555     Document Type: Article

References (16)

1. K. Ng and J. Brews, Measuring the effective channel length of MOSFET's, IEEE Circuits and Devices, pp. 33-38, Nov. 1990.
2. G. Hu, C. Chang, and Y. Chia, Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET, IEEE Trans. Electron Devices, Vol. ED34, pp. 2469-2475, Dec. 1987.
3. S. E. Eaux, Accuracy of an effective channel length/external resistance extraction algorithm for MOSFET's, IEEE Trans. Electron Devices, Vol. ED31, pp. 1245-1251, Sept. 1984.
4. A. Azuma, T. Asamura, Y. Toyoshima, and M. Kakumu, Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET, in Proc. Symp. VLSI Technol, 1994, pp. 129-130.
5. C. Hao, B. Gabon-Till, S. Christoloveaunu, and G. Ghibaudo, Experimental determination of short-channel MOSFET parameters, SolidState Electron., vol. 28, no. 10, pp. 1025-1030, 1985.
6. C. McAndrew and P. Eayman, MOSFET effective channel length, VT and series resistance determination by robust optimization, IEEE Trans. Electron Devices, vol. 39, pp. 2298-2311, Oct. 1992.
7. J. Y. C. Sun, M. R. Wordeman, and S. E. Eaux, On the accuracy of channel length characterization of EDD MOSFET's, IEEE Trans. Electron Devices, Vol. ED33, pp. 1556-1562, Oct. 1986.
8. M. Wordeman, Geometry effects in MOSFET channel length extraction algorithms, IEEE Electron Device Lett., vol. 6, pp. 186-188, Apr. 1995.
9. S. Kubicek, S. Biesemans, Q. Wang, K. Maex, and K. De Meyer, Sub0.1 -ftm nMOSFET's fabricated using experimental design techniques to optimize performance and minimize process sensitivity, in Proc. Symp. VLSI Technol., 1995, pp. 105-106.
10. S. Biesemans, M. Hendriks, S. Kubicek, and K. De Meyer, Accurate determination of the gate voltage dependent effective channel length, series resistance, and source drain doping profile for optimization, in P roc. Symp. VLSI Technol, 1996, pp. 165-166.
11. P. Suciu and R. Johnston, Experimental derivation of the source and drain resistance of MOS transistors, IEEE Trans. Electron Devices, vol. 27, pp. 1846-1847, Sept. 1980.
12. K. Terada and H. Muta, A new method to determine effective MOSFET channel length, Jpn. J. Appl. Phys., vol. 18, no. 5, p. 953, 1979.
13. J. Chern, P. Chang, R. Motta, and N. Godinho, A new method to determine MOSFET channel length, IEEE Electron Device Lett., Vol. EDL1, pp. 170-173, Sept. 1980.
14. F. Whitfield, A modification on an improved method to determine MOSFET channel length, IEEE Electron Device Lett., vol. 6, pp. 109-110, Mar. 1985.
15. Y. Taur, D. Zicherman, D. Lombard!, P. Restle, C. Hsu, H. Hanafi, M. Wordeman, B. Davari, and G. Shahidi, A new shift and ratio method for MOSFET channel length extraction, IEEE Electron Device Lett., vol. 13, pp. 267-269, May 1992.
16. S. Bieseman and K. De Meyer, Comparison of an L-array and a single transistor method to extract Le(f and Rs in deep submicron MOSFET's, in Proc. ESSDERC Conf., Stuttgart, Germany, Sept. 22-24, 1997, pp. 660-663.