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Volumn 13, Issue 5, 1992, Pages 267-269

A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS, CMOS;

EID: 0026869985     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.145049     Document Type: Article
Times cited : (194)

References (10)
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    • (1974) IEEE J. Solid-State Circuits , vol.SC-9 , Issue.5 , pp. 256
    • Dennard, R.H.1
  • 3
    • 0024143472 scopus 로고
    • Measurement of threshold voltage and channel length of submicron MOSFET's
    • S. Jain, “Measurement of threshold voltage and channel length of submicron MOSFET's,” Proc. Inst. Elec. Eng., vol. 135-1, no. 6, p. 162, 1988.
    • (1988) Proc. Inst. Elec. Eng. , vol.135-1 , Issue.6 , pp. 162
    • Jain, S.1
  • 4
    • 84949083566 scopus 로고
    • On the accuracy of channel length characterization of LDD MOSFET's
    • J. Y.-C. Sun, M. R. Wordeman, and S. E. Laux, “On the accuracy of channel length characterization of LDD MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, no. 10, p. 1556, 1986.
    • (1986) IEEE Trans. Electron Devices , vol.ED-33 , Issue.10 , pp. 1556
    • Sun, J.Y.C.1    Wordeman, M.R.2    Laux, S.E.3
  • 6
    • 0025455892 scopus 로고
    • Experimental technology and performance of 0.1- μm-gate-length FET's operated at liquid-nitrogen temperature
    • G. A. Sai-Halasz et al., “Experimental technology and performance of 0.1- μm-gate-length FET's operated at liquid-nitrogen temperature,” IBM J. Res. Develop., vol. 34, no. 4, p. 452, 1990.
    • (1990) IBM J. Res. Develop. , vol.34 , Issue.4 , pp. 452
    • Sai-Halasz, G.A.1
  • 7
    • 0022751618 scopus 로고
    • Analysis of the gate-voltage-dependent series resistance of MOSFET's
    • K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, no. 7, p. 965, 1986.
    • (1986) IEEE Trans. Electron Devices , vol.ED-33 , Issue.7 , pp. 965
    • Ng, K.K.1    Lynch, W.T.2
  • 8
    • 0023313303 scopus 로고
    • Source-drain contact resistance in CMOS with self-aligned TiSi2
    • Y. Taur et al., “Source-drain contact resistance in CMOS with self-aligned TiSi2,” IEEE Trans. Electron Devices, vol. ED-34, no. 3, p. 575, 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-34 , Issue.3 , pp. 575
    • Taur, Y.1
  • 9
  • 10
    • 0024718053 scopus 로고
    • MOS device modeling at 77 K
    • S. Selberherr, “MOS device modeling at 77 K,” IEEE Trans. Electron Devices, vol. 36, no. 8, p. 1464, 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , Issue.8 , pp. 1464
    • Selberherr, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.