Sub 0.1 μm nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1995, Pages 105-106

  Kubicek, S ^a   Biesemans, S ^a   Wang, Q F ^a   Maex, K ^a   De Meyer, K ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; ELECTRIC CURRENTS; ELECTRON BEAM LITHOGRAPHY; INDIUM; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; OPTIMIZATION; PERFORMANCE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SENSITIVITY ANALYSIS;

DESIGN OF EXPERIMENTS; DEVICE PERFORMANCE; INDIUM CHANNEL IMPLANT; POLY LINE; PROCESS SENSITIVITY; SALICIDATION; SHEET RESISTANCE; SHORT CHANNEL EFFECT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0029513733     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)