Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1994, Pages 129-130

  Azuma, A ^a   Asamura, T ^a   Toyoshima, Y ^a   Kakumu, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; ELECTRIC CURRENTS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR JUNCTIONS;

EXTRAPOLATION; GATE BIAS; GATE LENGTH; PARASITIC RESISTANCE;

ELECTRIC RESISTANCE MEASUREMENT;

EID: 0028554604     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)