Nonscan design-for-testability techniques using rt-level design information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 12, 1997, Pages 1488-1506

  Dey, Sujit ^a   Potkonjak, Miodrag ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

At speed testing; Data paths; K level testable; Nonscan; Test points; Testability measure

Indexed keywords

DATA TRANSFER; DESIGN; EFFICIENCY; GRAPH THEORY; TESTING;

TESTABILITY;

NETWORKS (CIRCUITS);

EID: 0031349899     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.664230     Document Type: Article

References (53)

1. K. Cheng and V. Agrawal, "A partial scan method for sequential circuits with feedback," IEEE Trans. CompuL, vol. 39, pp. 544-548, Apr. 1990.
2. D. Lee and S. Reddy, "On determining scan flip-flops in partial-scan designs," in Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 322-325.
3. V. Chickermane and J.H. Patel, "An optimization based approach to the partial scan design problem," in Proc. Int. Test Conf., Sept. 1990, pp. 377-386.
4. S. Reddy and R. Dandapani, "Scan design using standard flip-flops," IEEE Design Test Comput. Mag., pp. 52-54, Feb. 1987.
5. S. Narayanan and M. Breuer, "Reconfigurable scan chains: A novel approach to reduce test application time," in Proc. ICCAD, 1993, pp. 710-715.
6. P. Maxwell, R. Aitken, V. Johansen, and I. Chiang, "The effect of different test sets on quality level prediction: When is 80% better than 90%?" in Proc. Int. Test Conf., Oct. 1991, pp. 358-364.
7. J. Heyes and A. Friedman, "Test point placement to simplify fault detection," in Proc. 1973 Symp. Fault-Tolerant Computing (FTCS), 1973, pp. 73-78.
8. K. Saluja and S. Reddy, "On minimally testable logic networks," IEEE Trans. Comput., vol. C-23, no. 11, pp. 1204-1207, 1974.
9. B. Krishnamurthy, "A dynamic programming approach to the test point insertion problem," in Proc. 24th Design Automation Conf., 1987, pp. 695-705.
10. I. Pomeranz and Z. Kohavi, "Polynomial complexity algorithms for increasing testability of digital circuits by testing-module insertion," IEEE Trans. Comput., vol. 40, no. 11, pp. 1198-1212, 1991.
11. I. Pomeranz and S. Reddy, "Design-for-testability for path delay faults in large combinational circuits using test points," in Proc. 31st Design Automation Conf., 1994, pp. 358-364.
12. J. Stewart, "Future testing of large LSI circuit cards," in Semiconductor Test Symp., 1973, pp. 6-17.
13. T. Gheewala, "Crosscheck: A cell based VLSI testability solution," in Proc. DAC, 1989, pp. 706-709.
14. S. Chandra, T. Ferry, T. Gheewala, and K. Pierce, "ATPG based on a novel grid-addressable latch element," in Proc. DAC, 1991, pp. 282-286.
15. V. Chickermane, E. Rudnick, P. Banerjee, and J.H. Patel, "Non-scan design-for-testability techniques for sequential circuits," in Proc. Design Automation Conf., June 1993, pp. 236-241.
16. E. Rudnick, V. Chickermane, and J. Patel, "An observability enhance-ment approach for improved testability and at-speed test," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1051-1056, Aug. 1994.
17. S.S. K. Chiu and C. Papachristou, " A built-in self-testing approach for minimizing hardware overhead," in Proc. Int. Conf. Computer Design, 1991, pp. 282-285.
18. L. Avra, " Allocation and assignment in high-level synthesis for self-testable data paths," in Proc. Int. Test Conf., 1991, pp. 463-472.
19. L. Avra and E. McCluskey, "Synthesizing for scan dependence in built-in self-testable designs," in Proc. Int. Test Conf., Oct. 1993, pp. 734-743.
20. I. Harris and A. Orailoglu, "Microarchitectural synthesis of VLSI designs with high test concurrency," in Proc. Design Automation Conf., June 1994, pp. 206-211.
21. C.-H. Chen, T. Karnik, and D.G. Saab, "Structural and behavioral synthesis for testability techniques," IEEE Trans. Computer-Aided Design, vol. 13, pp. 777-785, June 1994.
22. A. Majumdar, R. Jain, and K. Saluja, "Incorporating testability considerations in high-level synthesis," J. Electron. Testing: Theory Appl, pp. 43-55, Feb. 1994.
23. T.C. Lee, W. Wolf, N. K. Jha, and J. M. Acken, "Behavioral synthesis for easy testability in data path allocation," in Proc. Int. Conf. Computer Design, 1992, pp. 29-32.
24. T.C. Lee, W. H. Wolf, and N. K. Jha, "Behavioral synthesis for easy testability using data path scheduling," in Proc. Int. Conf. Computer-Aided Design, 1992, pp. 616-619.
25. T.C. Lee, N. K. Jha, and W. H. Wolf, "Behavioral synthesis of highly testable data paths under nonscan and partial scan environments," in Proc. Design Automation Conf., 1993, pp. 292-297.
26. S. Dey, M. Potkonjak, and R. Roy, "Exploiting hardware sharing in high level synthesis for partial scan optimization," in Proc. Int. Conf. Computer-Aided Design, Nov. 1993, pp. 20-25.
27. S. Dey and M. Potkonjak, "Transforming behavioral specifications to facilitate synthesis of testable designs," in Proc. Int. Test Conf., Oct. 1994, pp. 184-193.
28. T. Thomas, P. Vishakantaiah, and J. Abraham, "Impact of behavioral modifications for testability," in Proc. 12th IEEE VLSI Test Symp. Apr. 1994, pp. 427-432.
29. C.-H. Chen, C. Wu, and D.G. Saab, "BETA: Behavioral testability analysis," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 202-205.
30. P. Vishakantaiah and J. Abraham, "High level testability analysis using VHDL descriptions," in Proc. EDAC, Feb. 1993, pp. 170-174.
31. C.H. Gebotys and M. I. Elmasry, "Integration of algorithmic VLSI synthesis with testability incorporation," IEEE J. Solid-State Circuits, vol. 24, pp. 45862, Apr. 1989.
32. S. Bhattacharya, F. Brglez, and S. Dey, "Transformations and resynthesis for testability of RT-level control-data path specifications," IEEE Trans. VLSI Syst., vol. 1, pp. 304-318, Sept. 1993.
33. V. Chickermane, J. Lee, and J. Patel, "Addressing design for testability at the architectural level," IEEE Trans. Computer-Aided Design, vol. 13, pp. 920-934, July 1994.
34. J. Steensma, F. Catthoor, and H.D. Man, " Partial scan at the register-transfer level," in Proc. Int. Test Conf., Oct. 1991, pp. 488-497.
35. H. Harmanani and C. Papachristou, "An improved method for RTL synthesis with testability tradeoffs," in Proc. Int. Conf. Computer-Aided Design, Nov. 1993, pp. 30-35.
36. K. Wagner and S. Dey, "High level synthesis for testability: A survey and perspective," in Proc. Design Automation Conf., June 1996, pp. 131-136.
37. S. Dey, V. Gangaram, and M. Potkonjak, "A controller-based design-for-testability technique for controller-data path circuits," in Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp. 534-540.
38. H.D. M. et al, "Synthesis of DSP systems at Leuven," in Proc. IEEE ICCD, 1987, pp. 133-145.
39. J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Design Test Comput. Mag., pp. 40-51, 1991.
40. D. Patterson and J. Hennessy, Computer Architecture: A Quantitative Approach. San Mateo, CA: Kaufman, 1989.
41. T.M. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits," in Proc. EDAC, 1991, pp. 214-218.
42. H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. Comput., vol. C-32, pp. 1137-1144, Dec. 1983.
43. T. Kirkland and M. Mercer, "A topological search algorithm for ATPG," in 24th Design Automation Conf. (ACM/IEEE), June 1987, pp. 502-508.
44. F. Maamari and J. Rajski, "A method of fault simulation based on stem regions," IEEE Trans. Computer-Aided Design, vol. 9, pp. 212-220, Feb. 1990.
45. H. Fujiwara, "Computational complexity of controllability/observability problems for combinational circuits," IEEE Trans. Comput., vol. 39, pp. 762-767, June 1990.
46. S. Dey, F. Brglez, and G. Kedem, "Corolla based circuit partitioning and resynthesis," in Proc. 27th ACM/IEEE Design Automation Conf., June 1990, pp. 607-612.
47. C.H. Papadimitriou and K. Steiglitz, Combinatorial Optimization Algorithms and Complexity. Englewood Cliffs, NJ: Prentice-Hall, 1982.
48. R. Haddad and T. Parsons, Digital Signal Processing: Theory, Applications and Hardware. New York: Computer Science, 1991.
49. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 328-333.
50. S. Yang, " Logic synthesis and optimization benchmarks, user guide version 3.0," in Proc. Int. Workshop Logic Synthesis, Microelectronics Center of North Carolina, Research Triangle Park, NC, May 1991.
51. M. Garey and D. Johnson, Computers and Intractibility: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
52. R. Karp, "Reducibility among combinatorial problems," in Complexity of Computer Computations, R. Miller and J. Thatcher, Eds. New York: Plenum, 1972, pp. 85-103.
53. T. Cormen, C. Leiserson, and R. Rivest, Introduction to Algorithms. Cambridge, MA: MIT Press, 1990.