Exploiting hardware sharing in high-level synthesis for partial scan optimization

Volumn , Issue , 1993, Pages 20-25

  Dey, Sujit ^a   Potkonjak, Miodrag ^a   Roy, Rabindra K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DIGITAL FILTERS; ELECTRIC NETWORK SYNTHESIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; SHIFT REGISTERS;

AUTOMATIC TEST PATTERN GENERATION; CONTROL DATA FLOW GRAPH; PARTIAL SCAN OPTIMIZATION; SCAN REGISTERS; SEQUENTIAL TEST GENERATION COMPLEXITY;

SEQUENTIAL CIRCUITS;

EID: 0027876959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)