Computational Complexity of Controllability/Observability Problems for Combinational Circuits

IEEE Transactions on Computers

Volumn 39, Issue 6, 1990, Pages 762-767

  Fujiwara, Hideo ^a  

^a MEIJI UNIVERSITY   (Japan)

Author keywords

Computational complexity; controllability observability; design for testability; fault detection; NP complete; polynomial time algorithms; test generation

Indexed keywords

LOGIC CIRCUITS, COMBINATORIAL--ANALYSIS; SWITCHING THEORY--COMBINATORIAL SWITCHING;

COMPUTATIONAL COMPLEXITY; CONTROLLABILITY; DESIGN FOR TESTABILITY; FAULT DETECTION; OBSERVABILITY;

AUTOMATA THEORY;

EID: 0025445194     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.53597     Document Type: Article

References (6)

1. H. Fujiwara, Logic Testing and Design for Testability. Cambridge, MA: MIT Press, 1985.
2. P. H. Ibarra and S. K. Sahni, “Polynomially complete fault detection problems,” IEEE Trans. Comput., vol. C-24, pp. 242–249, Mar. 1975.
3. H. Fujiwara and S. Toida, “The complexity of fault detection problems for combinational logic circuits,” IEEE Trans. Comput., vol. C-31, pp. 555–560, June 1982.
4. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
5. S. A. Cook, “The complexity of theorem proving procedures,” in Proc. 3rd ACM Symp. Theory Comput., 1971, pp. 151–158.
6. H. Fujiwara and S. Toida, “The complexity of fault detection problems for combinational logic circuits,” Dep. Syst. Design, Univ. of Waterloo, Waterloo, Ont., Canada, Tech. Rep. 78-P-HW-150681, June 1981.