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Volumn , Issue , 1994, Pages 206-211
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Microarchitectural synthesis of VLSI designs with high test concurrency
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMPUTER HARDWARE;
ELECTRIC NETWORK SYNTHESIS;
ELECTRIC WIRING;
ESTIMATION;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUIT TESTING;
MICROPROCESSOR CHIPS;
SCHEDULING;
SHIFT REGISTERS;
HARDWARE SHARING CONFLICTS;
MICROARCHITECTURAL SYNTHESIS;
MULTI INPUT SIGNATURE REGISTERS;
PSEUDO RANDOM PATTERN GENERATORS;
REGISTER TRANSFER LEVEL;
VLSI CIRCUITS;
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EID: 0028602206
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/196244.196353 Document Type: Conference Paper |
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Times cited : (32)
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References (15)
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