An Observability Enhancement Approach for Improved Testability and At-Speed Test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 8, 1994, Pages 1051-1056

  Rudnick, Elizabeth M ^a   Patel, Janak H ^a   Chickermane, Vivek ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; ERRORS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OBSERVABILITY; SEQUENTIAL CIRCUITS; SEQUENTIAL MACHINES; SIMULATORS; TREES (MATHEMATICS);

AT SPEED TEST; EXCLUSIVE OR TREES; FAULT EFFECTS; FAULTS; TESTABILITY;

INTEGRATED CIRCUIT TESTING;

EID: 0028484273     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.298041     Document Type: Article

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