Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64K × 1 NMOS SRAMs

IEEE Transactions on Nuclear Science

Volumn 35, Issue 6, 1988, Pages 1673-1677

  Song, Y ^a   Vu, K N ^a   Cable, J S ^a   Witteles, A A ^a   Kolasinski, W A ^b   Koga, R ^b   Elder, J H ^b   Osborn, J V ^b   Martin, R C ^c   Ghoniem, N M ^c  

^a NORTHROP GRUMMAN CORPORATION   (United States)

^b AEROSPACE CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL--RANDOM ACCESS; INTEGRATED CIRCUITS; SEMICONDUCTING SILICON;

MULTIPLE BIT UPSETS; POLYSILICON; SINGLE EVENT UPSETS;

SEMICONDUCTOR DEVICES, MOS;

EID: 20244378808     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.25520     Document Type: Article

References (5)

1. S.E. Diehl-Nagle, “A New Class of Single Event Soft Errors,” IEEE Trans. Nucl. Sci., Vol. NS-31, pp. 1145–1148, 1984.
2. Similar phenomena have been observed in DRAMs. For instance, see J.A. Zoutendyk, et al., “Lateral Charge Transport from Heavy-Ion Tracks in IC Chips,” Poster Paper PJ-8, in the 1988 IEEE NSREC, Portland, Oregon, July, 1988.
3. P.M. Carter and B.R. Wilkins, “Influences on Soft Error Rates in Static RAM's,” IEEE J. Solid-State Circ., Vol. SC-22, pp. 430–436, 1987.
4. R.C. Martin, et al., “The Size Effect of Ion Charge Tracks on Single Event Multiple Bit Upset,” IEEE Trans. Nucl. Sci., Vol. NS-34, pp. 1305–1309, 1987.
5. For instance, see J.S. Fu, et al., “Comparison of 2D Memory SEU Transport Simulation with Experiments,” IEEE Trans. Nucl. Sci., Vol. NS-32, pp. 4145–4149, 1985.