-
4
-
-
48149108746
-
New non-volatile memory structures for FPGA architectures
-
Jul.
-
D. Choi et al., "New non-volatile memory structures for FPGA architectures," IEEE VLSI Syst., vol. 16, no. 7, pp. 874-881, Jul. 2008.
-
(2008)
IEEE VLSI Syst.
, vol.16
, Issue.7
, pp. 874-881
-
-
Choi, D.1
-
5
-
-
84890865306
-
Design of a process-variation-aware nonvolatile MTJ-based lookup-table circuit
-
D. Suzuki et al., "Design of a process-variation-aware nonvolatile MTJ-based lookup-table circuit," in Ext. Abstr. 2010 Int. Conf. Solid-State Devices and Materials, 2010, pp. 1146-1147.
-
(2010)
Ext. Abstr. 2010 Int. Conf. Solid-State Devices and Materials
, pp. 1146-1147
-
-
Suzuki, D.1
-
6
-
-
70449359801
-
Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an imme-diate-power-up field programmable gate array
-
D. Suzuki et al., "Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an imme-diate-power-up field programmable gate array," in Proc. VLSI Circuits Symp., 2006, pp. 80-81.
-
(2006)
Proc. VLSI Circuits Symp.
, pp. 80-81
-
-
Suzuki, D.1
-
7
-
-
57849093166
-
Nonvolatile magnetic flip-flop for standby-power-free SoCs
-
N. Sakimura et al., "Nonvolatile magnetic flip-flop for standby-power-free SoCs," in Proc. CICC, 2008, pp. 355-358.
-
(2008)
Proc. CICC
, pp. 355-358
-
-
Sakimura, N.1
-
8
-
-
0038444043
-
A ferroelectric memory-based secure dynamically programmable gate array
-
May
-
S. Masui et al., "A ferroelectric memory-based secure dynamically programmable gate array," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 715-725, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 715-725
-
-
Masui, S.1
-
9
-
-
79955743810
-
Programmable cell array using rewritable solid-electolyte switch integrated in 90 nm CMOS
-
M. Miyamura et al., "Programmable cell array using rewritable solid-electolyte switch integrated in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 228-229.
-
(2011)
IEEE ISSCC Dig. Tech. Papers
, pp. 228-229
-
-
Miyamura, M.1
-
10
-
-
84860673822
-
Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory
-
Y. Y. Liauw et al., "Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 406-407.
-
(2012)
IEEE ISSCC Dig. Tech. Papers
, pp. 406-407
-
-
Liauw, Y.Y.1
-
11
-
-
84876143641
-
Highly reliable, complementary atom switch (CAS) with low programming voltage embedded in Cu BEOL for nonvolatile programmable logic
-
M. Tada et al., "Highly reliable, complementary atom switch (CAS) with low programming voltage embedded in Cu BEOL for nonvolatile programmable logic," in IEDM Tech Dig., 2011, pp. 689-692.
-
(2011)
IEDM Tech Dig.
, pp. 689-692
-
-
Tada, M.1
-
13
-
-
67649970910
-
A 1.6 mm 4, 096 logic elements multi-context FPGA core in 90 nm CMOS
-
N. Miyamoto and T. Ohmi, "A 1.6 mm 4, 096 logic elements multi-context FPGA core in 90 nm CMOS," in Proc. IEEE Asian Solid-State Circuits Conf., 2008, pp. 89-92.
-
(2008)
Proc. IEEE Asian Solid-State Circuits Conf.
, pp. 89-92
-
-
Miyamoto, N.1
Ohmi, T.2
-
14
-
-
39049161506
-
Determination of power gating granularity for FPGA fabric
-
A. Rahman et al., "Determination of power gating granularity for FPGA fabric," in Proc. IEEE CICC, 2006, pp. 9-12.
-
(2006)
Proc. IEEE CICC
, pp. 9-12
-
-
Rahman, A.1
-
15
-
-
84885912734
-
Research, development, and application of crystalline oxide semiconductor
-
S. Yamazaki et al., "Research, development, and application of crystalline oxide semiconductor," in Proc. SID, 2012, pp. 183-186.
-
(2012)
Proc. SID
, pp. 183-186
-
-
Yamazaki, S.1
-
16
-
-
80755188153
-
Low power LC display using In-Ga-Zn-oxide FETs based on variable frame frequency
-
S. Amano et al., "Low power LC display using In-Ga-Zn-oxide FETs based on variable frame frequency," in Proc. SID, 2010, pp. 626-629.
-
(2010)
Proc. SID
, pp. 626-629
-
-
Amano, S.1
-
17
-
-
84877283890
-
New threshold voltage compensation pixel circuits in 13.5-inch quad full high definition OLED display of crystalline In-Ga-Zn-oxide FETs
-
T. Tanabe et al., "New threshold voltage compensation pixel circuits in 13.5-inch quad full high definition OLED display of crystalline In-Ga-Zn-oxide FETs," in Proc. SID, 2012, pp. 88-91.
-
(2012)
Proc. SID
, pp. 88-91
-
-
Tanabe, T.1
-
18
-
-
84860859738
-
High reliable In-Ga-Zn-oxide FET based electronic global shutter sensors for in-cell optical touch screens and image sensors
-
H. Tamura et al., "High reliable In-Ga-Zn-oxide FET based electronic global shutter sensors for in-cell optical touch screens and image sensors," in Proc. SID, 2011, pp. 729-732.
-
(2011)
Proc. SID
, pp. 729-732
-
-
Tamura, H.1
-
19
-
-
79959947256
-
1 Mb non-volatile random access memory using oxide semiconductor
-
T. Matsuzaki et al., "1 Mb non-volatile random access memory using oxide semiconductor," in Proc. 3rd IEEE Int. Memory Workshop, 2011, pp. 185-188.
-
(2011)
Proc. 3rd IEEE Int. Memory Workshop
, pp. 185-188
-
-
Matsuzaki, T.1
-
20
-
-
84865474287
-
Nonvolatile memory with extremely low-leakage indium-gallium-zinc-oxide thin-film transistor
-
Sep.
-
H. Inoue et al., "Nonvolatile memory with extremely low-leakage indium-gallium-zinc-oxide thin-film transistor," IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2258-2265, Sep. 2012.
-
(2012)
IEEE J. Solid-State Circuits
, vol.47
, Issue.9
, pp. 2258-2265
-
-
Inoue, H.1
-
21
-
-
84883703384
-
Multi-level cell memory with high-speed, low-voltage writing and high endurance using crystalline In-Ga-Zn oxide thin film transistor
-
T. Ishizu et al., "Multi-level cell memory with high-speed, low-voltage writing and high endurance using crystalline In-Ga-Zn oxide thin film transistor," in Ext. Abstr. SSDM 2012, 2012, pp. 590-591.
-
(2012)
Ext. Abstr. SSDM 2012
, pp. 590-591
-
-
Ishizu, T.1
-
22
-
-
84883738052
-
A 3 bit/cell nonvolatile memory with crystalline In-Ga-Zn-O TFT
-
S. Nagatsuka et al., "A 3 bit/cell nonvolatile memory with crystalline In-Ga-Zn-O TFT," in Proc. 5th IEEE Int. Memory Workshop, 2013, pp. 188-191.
-
(2013)
Proc. 5th IEEE Int. Memory Workshop
, pp. 188-191
-
-
Nagatsuka, S.1
-
23
-
-
84885624546
-
Eight-bit CPU with nonvolatile registers capable of holding data for 40 days at 85 C using crystalline In-Ga-Zn oxide thin film transistors
-
T. Ohmaru et al., "Eight-bit CPU with nonvolatile registers capable of holding data for 40 days at 85 C using crystalline In-Ga-Zn oxide thin film transistors," in Ext. Abstr. SSDM 2012, 2012, pp. 1144-1145.
-
(2012)
Ext. Abstr. SSDM 2012
, pp. 1144-1145
-
-
Ohmaru, T.1
-
24
-
-
84881334637
-
Processor with 4.9-s break-even time in power gating using crystalline In-Ga-Zn-oxide transistor
-
H. Kobayashi et al., "Processor with 4.9-s break-even time in power gating using crystalline In-Ga-Zn-oxide transistor," in COOL Chips XVI, Session VI, 2013.
-
(2013)
COOL Chips XVI, Session
, vol.6
-
-
Kobayashi, H.1
-
25
-
-
84903302000
-
A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors
-
K. Ohshima et al., "A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors," Jpn. J. Appl. Phys,., vol. 53, p. 04EE02, 2014.
-
(2014)
Jpn. J. Appl. Phys,.
, vol.53
, pp. 04EE02
-
-
Ohshima, K.1
-
26
-
-
84903312787
-
State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor
-
N. Sjökvist et al., "State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor," Jpn. J. Appl. Phys., vol. 53, p. 04EE10, 2014.
-
(2014)
Jpn. J. Appl. Phys.
, vol.53
, pp. 04EE10
-
-
Sjökvist, N.1
-
27
-
-
84904604118
-
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating
-
H. Tamura et al., "Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating," in COOL Chips XVII, Session VII, 2014.
-
(2014)
COOL Chips XVII, Session
, vol.7
-
-
Tamura, H.1
-
28
-
-
84905661937
-
A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm c-axis aligned crystalline In-Ga-Zn oxide transistor
-
A. Isobe et al., "A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm c-axis aligned crystalline In-Ga-Zn oxide transistor," in Proc. VLSI Circuits Symp., 2014, pp. 49-50.
-
(2014)
Proc. VLSI Circuits Symp.
, pp. 49-50
-
-
Isobe, A.1
-
29
-
-
80052689566
-
Electronic global shutter CMOS image sensor using oxide semiconductor FET with extremely low off-state current
-
T. Aoki et al., "Electronic global shutter CMOS image sensor using oxide semiconductor FET with extremely low off-state current," in Proc. VLSI Technology Symp., 2011, pp. 174-175.
-
(2011)
Proc. VLSI Technology Symp.
, pp. 174-175
-
-
Aoki, T.1
-
30
-
-
84885590122
-
Novel application of crystalline indium-gallium-zinc-oxide technology to LSI: Dynamically reconfigurable programmable logic device based on multi-context architecture
-
Y. Okamoto et al., "Novel application of crystalline indium-gallium-zinc-oxide technology to LSI: Dynamically reconfigurable programmable logic device based on multi-context architecture," ECS Trans., vol. 54, no. 1, pp. 141-149, 2013.
-
(2013)
ECS Trans.
, vol.54
, Issue.1
, pp. 141-149
-
-
Okamoto, Y.1
-
31
-
-
85027954911
-
A boosting pass gate with improved switching characteristics and no overdriving for programmable routing switch based on crystalline In-Ga-Zn-O technology
-
Y. Okamoto et al., "A boosting pass gate with improved switching characteristics and no overdriving for programmable routing switch based on crystalline In-Ga-Zn-O technology," IEEE VLSI Syst., vol. 23, no. 3, pp. 422-434, 2015.
-
(2015)
IEEE VLSI Syst.
, vol.23
, Issue.3
, pp. 422-434
-
-
Okamoto, Y.1
-
32
-
-
84890862030
-
Applications of crystalline indium-gallium-zinc-oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array
-
Y. Kurokawa et al., "Applications of crystalline indium-gallium-zinc-oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array," in Proc. Asia Symp. Quality Electronic Design, 2013, pp. 66-71.
-
(2013)
Proc. Asia Symp. Quality Electronic Design
, pp. 66-71
-
-
Kurokawa, Y.1
-
33
-
-
84898076937
-
Crystalline In-Ga-Zn-O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating
-
M. Kozuma et al., "Crystalline In-Ga-Zn-O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating," in Ext. Abstr. SSDM 2013, 2013, pp. 1096-1097.
-
(2013)
Ext. Abstr. SSDM
, vol.2013
, pp. 1096-1097
-
-
Kozuma, M.1
-
34
-
-
84903301856
-
Crystalline In-Ga-Zn-O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating
-
M. Kozuma et al., "Crystalline In-Ga-Zn-O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating," Jpn. J. Appl. Phys., vol. 53, p. 04EE12, 2014.
-
(2014)
Jpn. J. Appl. Phys.
, vol.53
, pp. 04EE12
-
-
Kozuma, M.1
-
35
-
-
84898079181
-
Normally-off computing with crystalline InGaZnO-based FPGA
-
T. Aoki et al., "Normally-off computing with crystalline InGaZnO-based FPGA," in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 502-503.
-
(2014)
IEEE ISSCC Dig. Tech. Papers
, pp. 502-503
-
-
Aoki, T.1
-
36
-
-
84856891628
-
Success in measurement the lowest off-state current of transistor in the world
-
Jun.
-
Y. Sekine et al., "Success in measurement the lowest off-state current of transistor in the world," ECS Trans., vol. 37, no. 1, pp. 77-88, Jun. 2011.
-
(2011)
ECS Trans.
, vol.37
, Issue.1
, pp. 77-88
-
-
Sekine, Y.1
-
37
-
-
84857332065
-
Evaluation of off-state current characteristics of transistor using oxide semiconductor material, indium-gallium-zinc oxide
-
Feb.
-
K. Kato et al., "Evaluation of off-state current characteristics of transistor using oxide semiconductor material, indium-gallium-zinc oxide," Jpn. J. Appl. Phys., vol. 51, no. 2, p. 021201, Feb. 2012.
-
(2012)
Jpn. J. Appl. Phys.
, vol.51
, Issue.2
, pp. 021201
-
-
Kato, K.1
-
38
-
-
84907708496
-
Scaling to 50-nm c-axis aligned crystalline In-Ga-Zn Oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory
-
Y. Kobayashi et al., "Scaling to 50-nm c-axis aligned crystalline In-Ga-Zn Oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory," in Proc. VLSI Technol. Symp., 2014, pp. 170-171.
-
(2014)
Proc. VLSI Technol. Symp.
, pp. 170-171
-
-
Kobayashi, Y.1
-
39
-
-
84939514562
-
A 128 kb 4 b/cell nonvolatile memory with crystalline In-Ga-Zn Oxide FET using Vt cancel write method
-
T. Matsuzaki et al., "A 128 kb 4 b/cell nonvolatile memory with crystalline In-Ga-Zn Oxide FET using Vt cancel write method," in IEEE ISSCC Dig. Tech. Papers, 2015, pp. 306-307.
-
(2015)
IEEE ISSCC Dig. Tech. Papers
, pp. 306-307
-
-
Matsuzaki, T.1
-
40
-
-
55449113158
-
-
Altera Co., San Jose, CA, USA
-
"Stratix Device Handbook," Altera Co., San Jose, CA, USA, 2006.
-
(2006)
Stratix Device Handbook
-
-
|