Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2014, Pages

  Kobayashi, Y ^a   Matsubayashi, D ^a   Nagatsuka, S ^a   Yakubo, Y ^a   Atsumi, T ^a   Shionoiri, Y ^a   Hondo, S ^a   Yamamoto, T ^a   Okazaki, Y ^a   Nagai, M ^a   Sasagawa, S ^a   Ito, D ^a   Hata, Y ^a   Hamada, T ^a   Arasawa, R ^a   Hanaoka, K ^a   Sakakura, M ^a   Suzawa, H ^a   Yamamoto, Y ^a   Yamazaki, S ^a  

^a SEMICONDUCTOR ENERGY LABORATORY CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; GALLIUM ALLOYS; II-VI SEMICONDUCTORS; INDIUM ALLOYS; REFRACTORY METAL COMPOUNDS; SEMICONDUCTING INDIUM COMPOUNDS; ZINC ALLOYS; ZINC OXIDE;

CHANNEL STRUCTURES; GATE ELECTRODES; INDIUM GALLIUM ZINC OXIDES; INSULATING FILM; ITS APPLICATIONS; OFF-STATE CURRENT; STORAGE CAPACITANCE; SUBTHRESHOLD CHARACTERISTICS;

GALLIUM COMPOUNDS;

EID: 84907708496     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2014.6894421     Document Type: Conference Paper

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9. TM"