New non-volatile memory structures for FPGA architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 7, 2008, Pages 874-881

  Choi, David ^a,b   Choi, Kyu ^c   Villasenor, John D ^a,b  

^a IEEE

^b Engineering IV   (United States)

^c O2IC Co Ltd   (United States)

Author keywords

Field programmable gate arrays (FPGAs); Non volatile memory

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; LOGIC DEVICES;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) LOGIC PROCESS; FPGA ARCHITECTURES; IMPROVED AREA; NON-VOLATILE; NON-VOLATILE MEMORY (NVM); OPERATIONAL VOLTAGES; PASS TRANSISTORS; POWER DOWN STRATEGIES; PROGRAMMABLE GATE ARRAY; PROGRAMMABLE LOGIC DEVICES (PLD); REPROGRAMMABLE; ROUTING SWITCHES; WIDE-RANGE;

REUSABILITY;

EID: 48149108746     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000461     Document Type: Article

References (15)

1. K.-T. Chang, W.-M. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K.-M. Chang, "A new SONOS memory using source-side injection for programming," IEEE Electron Devices Lett., vol. 19, no. 7, pp. 253-255, Jul. 1998.
2. Y. K. Lee, B. Y. Choi, J. S. Sim, K. W. Song, J. D. Lee, B.-G. Park, D. Park, and C. Chung, "A highly scalable split-gate SONOS flash memory with programmable-pass and pure-select transistors for sub-90-nm technology," in Proc. Int. Conf. Solid-State Devices Mater., Sep. 2004, pp. 252-253.
3. M. Rosmeulen, J. Van Houdt, L. Haspeslagh, and K. De Meyer, "Scanrom, a novel non-volatile memory cell storing 9 bits," in IEEE Symp. VLSI Tech. Dig., Jun. 2004, pp. 74-75.
4. T. Ogura, N. Ogura, M. Kirihara, K. Park, Y. Baba, M. Sekine, and K. Shimeno, "Embedded twin MONOS flash memories with 4 ns and 15 ns fast access time," in IEEE Symp. VLSI Circuits Dig., Jun. 2003, pp. 207-210.
5. K. H. Choi, "Non-volatile memory device," U.S. 6965 145, Nov. 15, 2005.
6. K. H. Choi, "Method of manufacturing self-aligned non-volatile memory device," U.S. 6972229, Dec. 6, 2005.
7. D. Choi, E.-P. Kwon, H. Lee, J. Chang, K. Choi, and J. Villasenor, "Single-chip integration of SRAM and non-volatile memory using bitline sharing," in Proc. Eur. Solid-State Circuits Conf., Sep. 2006, pp. 295-298.
8. Actel, "ProASIC3 Flash family FPGAs datasheet, Ver. 0.6," 2006, White Paper.
9. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for DeepSubmicron FPGAs. Boston, MA: Kluwer, 1999.
10. A. Gayasen, N. Vijaykrishnan, and M. Irwin, "Exploring technology alternatives for nano-scale FPGA interconnects," in Proc. Des. Autom. Conf, Jun. 2005, pp. 921-926.
11. S. Mohanty and V. K. Prasanna, "Duty cycle aware application design using FPGAs," in Proc. IEEE Symp. Field Program. Custom Comput. Mach., Apr. 2004, pp. 338-339.
12. T. Tuan, S. Kao, A. Rahman, S. Das, andS. Trimberger, "A 90nm low-power FPGA for battery-powered applications," in Proc. Int. Symp. Field Program. Gate Arrays, Feb. 2006, pp. 3-11.
13. D. J. Allred, W. Huang, V. Krishnan, H. Yoo, and D. V. Anderson, "An FPGA implementation for a high throughput adaptive filter using distributed arithmetic," in Proc. IEEE Symp. Field Program. Custom Comput. Mach., Feb. 2004, pp. 324-325.
14. Y. Lin, F. Li, and L. He, "Circuits and architectures for field programmable gate array with configurable supply voltage," IEEE Trans. Very Large Scale, Integr. (VLSI) Syst., vol. 13, no. 9, pp. 1035-1047, Sep. 2005.
15. J. Rose, R. J. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate array: The effect of logic block functionality on area efficiency," IEEE J. Solid-State Circuits, vol. 25, pp. 1217-1225, Oct. 1990.