Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 62, Issue 7, 2015, Pages 1757-1765

  Deng, Erya ^a,b   Zhang, Yue ^a,c   Kang, Wang ^a,c   Dieny, Bernard ^b   Klein, Jacques Olivier ^a   Prenat, Guillaume ^b   Zhao, Weisheng ^a,c  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CEA GRENOBLE   (France)

^c BEIHANG UNIVERSITY   (China)

Author keywords

3 D integration; 8 bit flip flop; 8 bit full adder; full non volatility; STT MTJ; synchronous

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; DELAY CIRCUITS; FIELD EFFECT TRANSISTORS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MEMORY ARCHITECTURE; THREE DIMENSIONAL INTEGRATED CIRCUITS; TUNNEL JUNCTIONS;

3-D INTEGRATION; FULL ADDERS; NONVOLATILITY; STT-MTJ; SYNCHRONOUS;

MAGNETIC DEVICES;

EID: 85027921973     PISSN: 15498328     EISSN: 15580806     Source Type: Journal    
DOI: 10.1109/TCSI.2015.2423751     Document Type: Article

References (32)

1. N. S. Kim et al., "Leakage current: Moore's law meets the static power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
2. International Roadmap for Semiconductor (ITRS) 2011, ERD Update.
3. C. Chappert, A. Fert, and F. Nguyen Van Dau, "The emergence of spin electronics in data storage," Nat. Mater., vol. 6, pp. 813-823, 2007.
4. J. P. Wang and X. Yao, "Programmable spintronic logic devices for reconfigurable computation and beyond history and outlook," J. Nanoelectron. Optoelectron., vol. 3, no. 1, pp. 12-23, Mar. 2008.
5. W. S. Zhao et al., "Synchronous non-volatile logic gate design based on resistive switching memories," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 2, pp. 443-454, Feb. 2014.
6. B. Engel et al., "A 4-Mb toggle MRAM based on a novel bit and switching method," IEEE Trans. Magn., vol. 41, no. 1, pp. 132-136, 2005.
7. B. Jovanovi?, R. M. Brum, and L. Torres, "A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design," J. Appl. Phys., vol. 115, p. 134316, Apr. 2014.
8. C. J. Lin et al., "45 nm Low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1 T/1MTJ cell," in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2009, pp. 1-4.
9. S. Ikeda et al., "Tunnel magnetoresistance of 604% at 300 K by suppression of Ta diffusion in CoFeB/MgO/CoFeB pseudo-spin-valves annealed at high temperature," Appl. Phys. Lett., vol. 93, no. 8, pp. 082508-3-082508-3, Aug. 2008.
10. M. Julliere, "Tunneling between ferromagnetic films," Phys. Lett. A, vol. 54, no. 3, pp. 225-226, Sep. 1975.
11. J. C. Slonczewski, "Current-driven excitation of magnetic multilayers," J. Magn. Magn. Mater., vol. 159, no. 1, pp. L1-L7, Jun. 1996.
12. L. Berger, "Emission of spin waves by a magnetic multilayer traversed by a current," Phy. Rev. B, vol. 54, pp. 9353-9358, Oct. 1996.
13. F. Zavaliche et al., "Electric field-induced magnetization switching in epitaxial columnar nanostructures," Nano Lett., vol. 5, no. 9, pp. 1793-1796, Aug. 2005.
14. I. L. Prejbeanu et al., "Thermally assisted switching in exchange-biased storage layer magnetic tunnel junctions," IEEE Trans. Magn., vol. 40, no. 4, pp. 2625-2627, Jul. 2004.
15. S. Ikeda et al., "A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction," Nat. Mater., vol. 9, no. 9, pp. 721-724, Jul. 2010.
16. E. Kitagawa et al., "Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU," in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2012, pp. 29.4.1-29.4.4.
17. G. Prenat et al., "CMOS/magnetic hybrid architectures," in Proc. IEEE Int. Conf. Electron. Circuits Syst. (ICECS), 2007, pp. 190-193.
18. D. Chabi et al., "Ultra low power magnetic flip-flop based on checkpointing/ power gating and self-enable mechanisms," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 6, pp. 1755-1765, Jun. 2014.
19. S. Onkaraiah et al., "Bipolar ReRAM based non-volatile flip-flops for low-power architectures," in Proc. IEEE Int. Conf. New Circuits Syst. (NEWCAS), 2012, pp. 417-420.
20. W. S. Zhao et al., "New non-volatile logic based on spin-MTJ," Physica Status Solidi a-Applications and Materials Science, vol. 6, no. 250, pp. 1373-1377, May 2008.
21. E. Y. Deng et al., "Low power magnetic full-adder based on spin transfer torque MRAM," IEEE Trans. Magn., vol. 49, no. 9, pp. 4982-4987, Sep. 2013.
22. S. Matsunaga et al., "Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions," Appl. Phys. Exp., vol. 1, no. 9, pp. 091301-1-091301-3, 2008.
23. Y. Gang, W. Zhao, J.-O. Klein, C. Chappert, and P. Mazoyer, "A highreliability, low-power magnetic full adder," IEEE Trans. Magn., vol. 47, no. 11, pp. 4611-4616, Nov. 2011.
24. F. Ren and D. Markovic, "True energy-performance analysis of the MTJ-based logic-in-memory architecture (1-bit full adder)," IEEE Trans. Electron Devices, vol. 57, no. 5, pp. 1023-1028, May 2010.
25. Y. Zhang et al., "Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junctions for memory and logic applications," IEEE Trans. Magn., vol. 49, no. 7, pp. 4375-4378, Jul. 2013.
26. Y. Zhang et al., "Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions," IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 819-826, Mar. 2012.
27. W. S. Zhao et al., "Spin transfer torque (STT)-MRAM based run time reconfiguration FPGA circuit," ACM Trans. Embedded Comput. Syst., vol. 9, no. 2, Oct. 2009, Art. 14.
28. W. C. Black and B. Das, "Programmable logic using giant-magneto resistance and spin-dependent tunneling devices," J. Appl. Phys., vol. 87, no. 9, pp. 6674-6679, 2000.
29. M. Hariyama, S. Ishihara, N. Idobata, and M. Kameyama, "Non-volatile multi-context FPGAs using hybrid multiple-valued/binary context switching signals," in Proc. Eng. Reconfigurable Syst. Algorithms (ERSA), 2008, pp. 309-310.
30. W. S. Zhao, C. Chappert, V. Javerliac, and J.-P. Noziere, "High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits," IEEE Trans. Magn., vol. 45, no. 10, pp. 3784-3787, 2009.
31. H. P. Trinh et al., "Magnetic adder based on racetrack memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 6, pp. 1469-1477, Jun. 2013.
32. E. Y. Deng et al., "Design optimization and analysis of multicontext STT-MTJ/CMOS logic circuits," IEEE Trans. Nanotechnol., vol. 14, no. 1, pp. 169-177, Jan. 2015.