A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 7, 2010, Pages 1018-1027

  Lee, Jongeun ^a   Shrivastava, Aviral ^b  

^a Ulsan National Institute of Science and Technology   (South Korea)

^b Arizona State University   (United States)

Author keywords

Compiler architecture hybrid; embedded processor design; energy; partially protected register file (PPRF); register file vulnerability (RFV); reliability

Indexed keywords

EID: 85008014183     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2049050     Document Type: Article

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