A compiler optimization to reduce soft errors in register files

ACM SIGPLAN Notices

Volumn 44, Issue 7, 2009, Pages 41-49

  Lee, Jongeun ^a   Shrivastava, Aviral ^a  

^a Arizona State University   (United States)

Author keywords

Architectural vulnerability factor; Compilation; Embedded system; Link time optimization; Register file; Soft error; Static analysis

Indexed keywords

EMBEDDED SYSTEMS; ERROR CORRECTION; HEURISTIC ALGORITHMS; PROGRAM COMPILERS; RADIATION HARDENING; STATIC ANALYSIS;

ARCHITECTURAL VULNERABILITY FACTOR; COMPILATION; LINK-TIME OPTIMIZATION; REGISTER FILES; SOFT ERROR;

INTEGER PROGRAMMING;

EID: 67650825001     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1543136.1542459     Document Type: Conference Paper

References (27)

1. Todd Austin. SimpleScalar LLC. URL http://www.simplescalar.com/.
2. Jason A. Blome, Shantanu Gupta, Shuguang Feng, and Scott Mahlke. Cost-efficient soft error protection for embedded microprocessors. In CASES '06, pages 421-431, 2006.
3. Kaiyu Chen, Sharad Malik, and David I. August. Retargetable static timing analysis for embedded software. In ISSS '01, pages 39-44, 2001.
4. M. Garey and D. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman, 1979.
5. M. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IWWC, pages 3-14, 2001.
6. M. Harrold, G. Rothermel, and S. Sinha. Computation of interpro-cedural control dependence. In Proc. ACM SIGSOFT Int'l Symp. on Software Testing and Analysis, pages 11-20, 1998.
7. ITRS. International technology roadmap for semiconductors 2007 executive summary. URL http://www.itrs.net/.
8. M. Kandala, W. Zhang, and L. Yang. An area-efficient approach to improving register file reliability against transient errors. In Proc. Int'l Conf. on Advanced Information Networking and Applications Workshops, pages 798-803, 2007.
9. B. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System Tech. Journal, 49:291-307, February 1970.
10. Israel Koren and C. Mani Krishna. Fault-Tolerant Systems. Morgan Kaufmann Publishers, 2007.
11. Jongeun Lee and Aviral Shrivastava. Compiler-managed register file protection for energy-efficient soft error reduction. In Proceedings of Asia and South Pacific Design Automation Conference, pages 618-623, 2009a.
12. Jongeun Lee and Aviral Shrivastava. Static analysis to mitigate soft errors in register files. In Proc. Int'l Conf. Design Automation and Test in Europe (DATE), 2009b.
13. Xiaodong Li, Sarita V. Adve, Pradip Bose, and Jude A. Rivers. Online estimation of architectural vulnerability factor for soft errors. SIGARCH Comput. Archit. News, 36(3):341-352, 2008.
14. G. Memik, M. H. Chowdhury, A. Mallik, and Y. I. Ismail. Engineering over-clocking: reliability-performance trade-offs for high-performance register files. Proc. Int'l Conf. on Dependable Systems and Networks, 2005.
15. Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, and Kee Sup Kim. Robust system design with built-in soft-error resilience. IEEE Computer, 38(2):43-52, 2005.
16. Pablo Montesinos, Wei Liu, and Josep Torrellas. Using register lifetime predictions to protect register files against soft errors. In DSN '07, pages 286-296, 2007.
17. Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proc. International Symposium on Microarchitecture, Dec 2003.
18. Nahmsuk Oh, Philip P. Shirvani, and Edward J. McCluskey. Control-flow checking by software signatures. IEEE Transactions on Reliability, 51:111-122, 2002a.
19. Nahmsuk Oh, Philip P. Shirvani, and Edward J. McCluskey. Error detection by duplicated instructions in super-scalar processors. IEEE Transactions on Reliability, 51:63-75, 2002b.
20. George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, and David I. August. SWIFT: Software implemented fault tolerance. In Int'l Symp. Code Generation and Optimization, pages 243-254, 2005.
21. Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, and Alexandru Nicolau. Operation tables for scheduling in the presence of incomplete bypassing. In CODES+ISSS, pages 194-199, 2004.
22. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankara-narayanan, and D. Tarjan. Temperature-aware microarchitecture. In Proc. Int'l Symp. on Computer Architecture, pages 2-13, 2003.
23. Timothy J. Slegel, Robert M. III Averill, Mark A. Check, Bruce C. Giamei, Barry W. Krumm, Christopher A. Krygowski, Wen H. Li, John S. Liptay, John D. MacDougall, Thomas J. McPher-son, Jennifer A. Navarro, Eric M. Schwarz, Kevin Shum, and Charles F. Webb. IBM's S/390 G5 microprocessor design. IEEE Micro, 19(2):12-23, 1999.
24. Kristen R. Walcott, Greg Humphreys, and Sudhanva Gurumurthi. Dynamic prediction of architectural vulnerability from microarchitectural state. SIGARCH CA News, (2):516-527, 2007.
25. Youfeng Wu and James Larus. Static branch frequency and program profile analysis. In MICRO 27, pages 1-11, 1994.
26. Jun Yan and Wei Zhang. Compiler-guided register reliability improvement against soft errors. In EMSOFT '05, pages 203-209, 2005.
27. K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 1996.