Bypass aware instruction scheduling for register file power reduction

ACM SIGPLAN Notices

Volumn 41, Issue 7, 2006, Pages 173-181

  Park, Sanghyun ^a   Nicolau, Alex ^b   Shrivastava, Aviral ^b   Paek, Yunheung ^a   Dutt, Nikil ^b   Earlie, Eugene ^c  

^a Seoul National University   (South Korea)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Architecture sensitive Compiler; Bypass sensitive; Forwarding Paths; Operation Table; Power Consumption; Processor Bypasses; Register File; Reservation Table

Indexed keywords

ARCHITECTURE-SENSITIVE COMPILERS; BYPASS-SENSITIVE; FORWARDING PATHS; OPERATION TABLE; POWER CONSUMPTION; PROCESSOR BYPASSES; REGISTER FILE; RESERVATION TABLE;

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DATA TRANSFER; PROGRAM COMPILERS;

SHIFT REGISTERS;

EID: 33748999034     PISSN: 03621340     EISSN: 03621340     Source Type: Journal    
DOI: 10.1145/1159974.1134675     Document Type: Article

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