Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq

2015 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015

Volumn , Issue , 2015, Pages

  Vipin, Kizheppatt ^a   Fahmy, Suhaib A ^b  

^a Mahindra University   (India)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adaptive systems; Computer architecture; Field programmable gate arrays; Hardware; Program processors; Runtime

Indexed keywords

ADAPTIVE SYSTEMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT DESIGN; NASA; PROGRAM PROCESSORS;

ALTERNATIVE CONFIGURATIONS; DYNAMICALLY ADAPTIVE SYSTEMS; ENVIRONMENTAL CONDITIONS; HARDWARE MODULES; PARTIAL RECONFIGURATION; RUNTIME FRAMEWORKS; RUNTIMES; SYSTEM CONFIGURATIONS;

RECONFIGURABLE HARDWARE;

EID: 84962492451     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2015.7231169     Document Type: Conference Paper

References (30)

1. B. H. Cheng, P. Sawyer, N. Bencomo, and J. Whittle, "A goal-based modeling approach to develop requirements of an adaptive system with environmental uncertainty," in Model Driven Engineering Languages and Systems. Springer Berlin Heidelberg, 2009, pp. 468-483.
2. H. Goldsby, P. Sawyer, N. Bencomo, B. H. C. Cheng, and D. Hughes, "Goal-based modeling of dynamically adaptive system requirements," in Proceedings of International Conference and Workshop on the Engineering of Computer Based Systems, 2008, pp. 36-45.
3. J. Mitola and G. Q. Maguire, "Cognitive radio: making software radios more personal," IEEE Personal Communications, vol. 6, no. 4, pp. 13-18, 1999.
4. T. Bapty, S. Neema, J. Scott, J. Sztipanovits, and S. Asaad, "Modelintegrated tools for the design of dynamically reconfigurable systems," VLSI Design, vol. 10, no. 3, pp. 281-306, 2000.
5. UG702: Partial Reconfiguration User Guide, Xilinx, 2010.
6. M. Bourgeault, "Altera's partial reconfiguration flow," Altera, Tech. Rep., 2011.
7. H. Walder, C. Steiger, and M. Platzner, "Fast online task placement on FPGAS: free space partitioning and 2D-hashing," in Proceedings of International Parallel and Distributed Processing Symposium (IPDPS), 2003.
8. K. Vipin, S. Shreejith, S. A. Fahmy, and A. Easwaran, "Mapping timecritical safety-critical systems to hybrid FPGAS," in Proceedings of the IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA), 2014, pp. 31-36.
9. J. Vidal, F. De Lamotte, G. Gogniat, J.-P. Diguet, and S. Guillet, "Dynamic applications on reconfigurable systems: from UML model design to FPGAS implementation," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011.
10. H. Kalte, G. Lee, M. Porrmann, and U. Ruckert, "REPLICA: A bitstream manipulation filter for module relocation in partial reconfigurable systems," in Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2005.
11. S. P. Fekete, J. C. van der Veen, A. Ahmadinia, D. Ghringer, M. Majer, and J. Teich, "Offline and online aspects of defragmenting the module layout of a partially reconfigurable device," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 9, pp. 1210-1219, Sept. 2008.
12. H. K. H. So and R. W. Brodersen, "Improving usability of FPGAbased reconfigurable computers through operating system support," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2006.
13. M. Santambrogio, V. Rana, and D. Sciuto, "Operating system support for online partial dynamic reconfiguration management," in Proc. of International Conf. on Field Programmable Logic and Applications (FPL), 2008, pp. 455-458.
14. E. Carvalho, N. Calazans, E. Briao, and F. Moraes, "PADReH- A framework for the design and implementation of dynamically and partially reconfigurable systems," in Proceedings of Symposium on Integrated Circuits and Systems Design (SBCCI), 2004, pp. 10-15.
15. A. Sohanghpurwala, P. Athanas, T. Frangieh, and A. Wood, "OpenPR: An open-source partial-reconfiguration toolkit for Xilinx FPGAS," in Proceedings of IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), 2011, pp. 228-235.
16. C. Beckhoff, D. Koch, and J. Torresen, "GoAhead: A partial reconfiguration framework," in Proceeding of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012, pp. 37-44.
17. A. Donato, F. Ferrandi, M. Redaelli, M. Santambrogio, and D. Sciuto, "Caronte: A methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms," in Proceedings of International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC), 2007, vol. 240, pp. 87-109.
18. M. Boden, T. Fiebig, M. Reiband, and P. Reichel, "GePaRD- A highlevel generation flow for partially reconfigurable designs," in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2008.
19. N. Abel, "Design and implementation of an object-oriented framework for dynamic partial reconfiguration," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2010.
20. H. Tan and R. DeMara, "A multilayer framework supporting autonomous run-time partial reconfiguration," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 504-516, May 2008.
21. S. Fahmy, J. Lotze, J. Noguera, L. Doyle, and R. Esser, "Generic software framework for adaptive applications on FPGAS," in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 55-62.
22. C. Bolchini, M. Carminati, A. Miele, and E. Quintarelli, "A framework to model self-adaptive computing systems," in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2013, pp. 71-78.
23. J. Lotze, S. Fahmy, J. Noguera, and L. Doyle, "A model-based approach to cognitive radio design," IEEE Journal on Selected Areas in Communications (JSAC), vol. 29, no. 2, pp. 455-468, Feb. 2011.
24. G. Kahn, "The semantics of a simple language for parallel programming," in Proceedings of the IFIP Congress, 1974, pp. 471-475.
25. M. Geilen and T. Basten, "Requirements on the execution of Kahn Process Networks," in Proceeding of European Symposium on Programming, 2003, pp. 319-334.
26. UG585: Zynq-7000 All Programmable SoC Technical Reference Manual, Xilinx, Mar. 2013.
27. K. Vipin and S. A. Fahmy, "Automated partitioning for partial reconfiguration design of adaptive systems," in Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops-Reconfigurable Architectures Workshop, 2013, pp. 172-181.
28. K. Vipin and S. A. Fahmy, "Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration," in Reconfigurable Computing: Architectures, Tools and Applications-Proceedings of Int. Symp. on Applied Reconfigurable Computing (ARC), 2012, pp. 13-25.
29. K. Vipin and S. A. Fahmy, "ZyCAP: Efficient partial reconfiguration management on the Xilinx Zynq," IEEE Embedded System Letters (ESL), vol. 6, no. 3, pp. 41-44, 2014.
30. CoPR GitHub public repository. [Online]. Available: https://github.com/archntu/copr/