GoAhead: A partial reconfiguration framework

Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012

Volumn , Issue , 2012, Pages 37-44

  Beckhoff, Christian ^a   Koch, Dirk ^a   Torresen, Jim ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

FPGA; GoAhead; Partial Reconfiguration; run time reconfiguration; Spartan 6

Indexed keywords

BIT STREAM; CONSTRAINT GENERATION; FLEXIBLE SYSTEM; FLOOR-PLANNING; GOAHEAD; IMPLEMENTATION PHASIS; LOW COSTS; LOW POWER; MIGRATION PATH; PARTIAL RECONFIGURATION; PARTIAL RUN-TIME RECONFIGURATION; RECONFIGURABLE MODULE; RECONFIGURABLE SYSTEMS; RUN TIME RECONFIGURATION; RUN-TIME RECONFIGURABLE; SCRIPTING INTERFACE; SPARTAN-6;

COMPUTERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84864962318     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2012.17     Document Type: Conference Paper

References (18)

1. S. N. und Anantha Chandrakasan, Leakage in Nanometer CMOS Technologies. Springer, 2006.
2. H. Kalte and M. Porrmann, "Context Saving and Restoring for Multitasking in Reconfigurable Systems," in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), aug 2005, pp. 223-228.
3. P. Athanas, J. Bowen, T. Dunham, C. Patterson, J. Rice, M. Shelburne, J. Suris, M. Bucciero, and J. Graf, "Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing," in International Conference on Field Programmable Logic and Applications (FPL). IEEE, August 2007, pp. 513-516.
4. G. Brebner, "The Swappable Logic Unit: A Paradigm for Virtual Hardware," in IEEE Symposium on FPGAs for Custom Computing Machines (FPGA), K. L. Pocek and J. Arnold, Eds., Los Alamitos, CA, April 1997, pp. 77-86.
5. P. Sedcole, B. Blodget, T. Becker, J. Anderson, and P. Lysaght, "Modular Dynamic Reconfiguration in Virtex FPGAs," IEE, vol. 153, no. 3, pp. 157-164, 2006.
6. Xilinx Inc., "Partial Reconfiguration User Guide (Rel 13.2)," 2011, available online: www.xilinx.com/support/documentation/sw-manuals/ xilinx13-2/ug702.pdf.
7. Mark Bourgeault, "Alteras Partial Reconfiguration Flow," 2011, available online: http://www.eecg.utoronto.ca/~jayar/FPGAseminar/FPGA- Bourgeault-June23-2011.pdf.
8. P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford, "Invited Paper: Enhanced Architecture, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs," in Proceedings of the 16th International Conference on Field Programmable Logic and Application (FPL), Aug 2006, pp. 1-6.
9. A. A. Sohanghpurwala, P. Athanas, T. Frangieh, and A. Wood, "Openpr: An open-source partial-reconfiguration toolkit for xilinx fpgas," in Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society, 2011, pp. 228-235.
10. D. Koch, C. Beckhoff, and J. Teich, "ReCoBus-Builder- a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs," in Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), Heidelberg, Germany, Sep. 2008, pp. 119-124.
11. S. Koh and O. Diessel, "COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs," in Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). Los Alamitos, CA, USA: IEEE Computer Society, 2006, pp. 273-274.
12. CosReCos project website: http://www.mn.uio.no/ifi/english/research/ projects/cosrecos/.
13. S. Yousuf and A. Gordon-Ross, "DAPR: Design Automation for Partially Reconfigurable FPGAs," in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, June 2010.
14. J. M. Carver, R. N. Pittman, and A. Forin, "Automatic Bus Macro Placement for Partially Reconfigurable FPGA Designs," in Proceeding of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). New York, NY, USA: ACM, 2009, pp. 269-272.
15. C. Beckhoff, D. Koch, and J. Torresen, "The Xilinx Design Language (XDL): Tutorial and Use Cases," in Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Montpellier, France, 2011, pp. 1-8.
16. N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, and M. French, "Torc: towards an open-source tool flow," in Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays (FPGA). ACM, 2011, pp. 41-44.
17. C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. E. Nelson, and B. Hutchings, "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs," in Proceedings of Int. Conf. on Field-Programmable Logic and Applications (FPL). IEEE, 2011, pp. 349-355.
18. D. Koch, C. Beckhoff, and J. Teich, "A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs," in Proceedings of the 17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). Monterey, California, USA: ACM, Feb. 2009, pp. 233-236.