REPLICA: A bitstream manipulation filter for module relocation in partial reconfigurable systems

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Kalte, H ^a   Lee, G ^a   Porrmann, M ^b   Ruckert U ^b  

^a UNIVERSITY OF WESTERN AUSTRALIA   (Australia)

^b UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BITSTREAM; FILTER ARCHITECTURE; GATE CAPACITY; PARTIAL RECONFIGURABLE SYSTEMS;

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATION; ONLINE SYSTEMS; RESOURCE ALLOCATION;

PARALLEL PROCESSING SYSTEMS;

EID: 33746310400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.380     Document Type: Conference Paper

References (11)

1. S. Hauck, Z. Li, E. J. Schwabe: Configuration Compression for the Xilinx XC6200 FPGA. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), Napa, CA, 1998.
2. M. J. Wirthlin and B. L. Hutchings. A dynamic instruction set computer. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1995.
3. Z. Li, S. Hauck: Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation. In Proceedings of the ACM/SIGDA Symposium on Field-Programmable Gate Arrays, Monterey, CA, 2002.
4. S. Sudhir, S. Nath, S. C. Goldstein: Configuration Caching and Swapping. In Proceedings of the 11th International Conference of Field-Programmable Logic and Applications (FPL), Belfast, Northern Ireland, UK, August 2001.
5. Xilinx, Inc.: Virtex-E FPGA Familiy Datasheet, 2001, URL: http://www.xilinx.xom
6. E. Horta, J. W. Lockwood. PARBIT: A tool to transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs), Tech. Rep. WUCS-01-13, Washington University, July 2001.
7. H. Kalte, M. Porrmann, and U. Rückert. System-on-programmable-chip approach enabling online fine-grained ID-placement. In Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), Santa F6, New Mexico, 2004.
8. Xilinx Application Notes 290: Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, 2002, http://www.xilinx.com.
9. H. Kalte, M. Porrmann and U. Rückert. A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
10. Xilinx Application Notes 151: Virtex Series Configuration Architecture User Guide, 2003, URL: http://www.xilinx.com.
11. H. Kalte, M. Köster, B. Kettelhoit, M. Porrmann, U. Rückert: A Comparative Study on System Approaches for Partially Reconfigurable Architectures. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04). Las Vegas, Nevada, June 2004.